United Microelectronics Corp.

Altasens, Inc.

Nien-Tsu Peng

Teng-Yuan Ko

Jhy-Jyi Sze

Chia-Huei Lin

Giuseppe Rossi

Tzeng-Fei Wen

Ju-Hsin Yen

Chien-Yao Huang

Water Lur

Kuen-Chu Chen

Bill Y Hsu

Chien-Chih Lin

Paul P Yen

An image sensor, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400&#xb0; C., and preferably contains metal material.

Image sensor

An image sensor and a method of manufacturing the same, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400&#xb0; C., and preferably contains metal material.

Image sensor and method of manufacturing the same

An image sensor includes a substrate, at least an optical device, at least a dielectric layer, and at least a wave-guide tube disposed upon the optical device. The wave-guide tube has an optical barrier disposed on a sidewall thereof and a filter layer filled in the wave-guide tube. The structure of the wave-guide tube has the advantages of shortening light path, focusing, and preventing undesirable crosstalk effect between different optical devices.

Image sensor with a waveguide tube and a related fabrication method

A method of manufacturing an interconnect on a wafer having an edge region and an interior region comprises the steps of: forming an insulating layer on the wafer having an interior region and an edge region; forming an opening penetrating through the insulating layer in the interior region and removing a portion of the insulating layer to expose a surface of the wafer in the edge region, simultaneously; forming a conductive layer over the insulating layer and the exposed surface of the wafer and filling the opening; and patterning the conductive layer to form a wire in the opening.

Method for improving wafer topography to provide more accurate transfer of interconnect patterns

A pad silicon oxide layer is deposited over the surface of a silicon substrate. A silicon nitride layer is deposited overlying the pad silicon oxide layer. Portions of the silicon nitride and pad silicon oxide layers not covered by a mask pattern are etched through and into the silicon substrate so as to provide a plurality of wide and narrow trenches within the silicon substrate that will form the device isolation regions. Channel-stops are selectively ion implanted through the openings into the substrate underneath the trenches. The silicon nitride and pad oxide layers are removed. A thin silicon oxide layer is grown conformally on all surfaces of the substrate and within the trenches. A thick layer of silicon oxide is deposited over the surface of the substrate completely filling the trenches wherein the thick silicon oxide layer is planarized over the narrow trenches but is not planarized over the wide trenches. The substrate is coated with a thick layer of photoresist and is subjected to a low dose flood exposure wherein the upper portion of the photoresist is exposed but the lower portion of the photoresist over the wide trenches is not exposed. The upper portion of the photoresist layer is developed and removed. The thick silicon oxide layer is anisotropically etched back to the surface of the substrate wherein the lower portion of the photoresist acts as a mask to prevent etching into the portion of the thick silicon oxide filling the wide trenches and completing the device isolation of the circuit.

Trench isolation with global planarization using flood exposure

Growing community of inventors

Hsin-Chu, Taiwan

Nien-Tsu Peng