United Microelectronics Corp.

Nien-Ting Ho

Kuo-Chih Lai

Shih-Min Chou

Chi-Mao Hsu

Yi-Wei Chen

Wei-Ming Hsiao

Chien-Chung Huang

Ti-Bin Chen

Ching-Yun Chang

Yen-Chen Chen

Yang-Ju Lu

Chin-Fu Lin

Hsin-Fu Huang

Chih-Chiang Wu

YI-Fan Li

Zhen Wu

Bor-Shyang Liao

Yun-Tzu Chang

Wen-Yen Huang

Chia Chang Hsu

Shu Min Huang

Szu-Yao Yu

Yu-Ru Yang

Min-Chuan Tsai

Hsiang-Chieh Yen

Min-Chung Cheng

Teng-Chun Tsai

Tsun-Min Cheng

Chia-Chang Hsu

Chien-Hao Chen

Wei-Yu Chen

Li-Han Chen

Huan-Chi Ma

Chien-Wen Yu

Kuan-Chun Lin

Chi-Yuan Sun

Hui-Hsin Hsu

Hui-Ting Lin

En-Chiuan Liou

Cheng-Hsien Chou

Ssu-I Fu

Yu-Ping Wang

Chun-Hsien Lin

Kuan-Cheng Su

Chung-Yi Chiu

Chih-Wei Yang

An-Chi Liu

Chien-Ming Lai

Shui-Yen Lu

Chih-Hao Yu

Yi-Wen Chen

Chao-Ching Hsieh

Chia-Fu Hsu

Shin-Chi Chen

Ya-Huei Tsai

Chih-Yueh Li

Yuan-Chi Pai

Jian-Cun Ke

Yao-Chang Wang

Tsung-Yin Hsieh

Yu-Ting Tseng

Sheng-Huei Dai

Tzung-Lin Li

Chi-Ju Lee

Hung-Yi Wu

Shu-Min Huang

Wei-Ning Chen

Yu-Feng Liu

Bao-Tzeng Huang

Main-Gwo Chen

Hsiao-Kwang Yang

Fang-Hong Yao

Yu-Hong Kuo

Yun Tzu Chang

Fang-Yi Liu

A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Field effect transistor and fabrication method thereof

A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Semiconductor device and method for fabricating the same

A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

Method for forming a thin film resistor with improved thermal stability

A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer and a titanium aluminide layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and a thickness of the titanium aluminide layer ranges from twice a thickness of the titanium nitride barrier layer to three times the thickness of the titanium nitride barrier layer.

An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

ReRAM structure and method of fabricating the same

A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first bottom barrier metal (BBM) layer on the first region and the second region; forming a first work function metal layer on the first BBM layer on the first region and the second region; removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.

A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

Manufacturing method of metal gate structure

A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Method for modulating work function of semiconductor device having metal gate structure by gas treatment

Growing community of inventors

Tainan, Taiwan

Nien-Ting Ho