Arm Limited

Invecas Technologies Pvt. Ltd

Synopsys, Inc.

Nidhir Kumar

Gyan Prakash

Sridhar Cheruku

Sivaramakrishnan Subramanian

Sandeep Dwivedi

Chandrashekar Narla

Muniswara Reddy Vorugu

Mikael Rien

Fabrice Blanc

Ranabir Dey

Manjunatha Govinda Prabhu

Praphul Malige

Tippana Hari Babu

A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges w both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address resister. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.

Method for cycle accurate data transfer in a skewed synchronous clock domain

A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations ire the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.

Method for calibrating the read latency of a DDR DRAM module

A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultaneously transmitted through the first delay circuit and the controllable delay circuit. Subsequently, the clock signals transmitted through the first delay circuit and the controllable delay circuit are captured at the output thereof, and fed as inputs to the phase detector circuitry. The phase detector circuitry determines whether the clock signals are in phase, and accordingly adjusts the delay associated with the controllable delay circuit until the two clock signals are determined to be in phase.

System and method for controlling phase alignment of clock signals

The present disclosure envisages an asynchronous clock gating circuitry and a method for designing the asynchronous clock gating circuitry. The asynchronous clock gating circuitry could be placed at the very beginning of the clock network, given its design and implementation logic. The asynchronous clock gating circuitry helps meet the timing requirement on the enable pin thereof. The asynchronous clock gating circuitry avoids cumbersome replication of cluck gating circuitry during physical implementation of the (circuit) design, and further helps reduce the power consumption levels in sequential circuits.

Asynchronous clock gating circuit

A method and system for multi cycle write leveling are disclosed. At least three data patterns are written into consecutive address locations of a memory device via corresponding write operations. Subsequently, predetermined beats of data strobe signals corresponding to certain predetermined write operations are gated. Based at least on the gating of predetermined data beats, a target data pattern to be read from the memory device is determined. Subsequently, a data read operation is performed, and the data written onto a specific address location of the memory device is read there from. The data thus read from the memory device is compared with the target pattern. Based on the comparison of the data read from the memory device with the target pattern, a delay cycle between the data strobe signals and clock signal is determined, and the data strobe signal and clock signal are accordingly calibrated.

System and method for multi-cycle write leveling

Interface circuitry transmitting transactions between an initiator and a recipient includes: a clock input receiving a clock signal; a transaction input receiving transactions; clock outputs for outputting the clock signal; transaction outputs outputting the transactions to the recipient; and synchronizing circuits clocked by the clock signal and transmitting the transactions to the transaction output in response to the clock signal. A controllable delay circuit is provided between the clock input and the synchronizing circuits. A further synchronizing circuit configured to provide a similar delay. Phase detection circuitry is arranged to detect alignment of the received clock signals. Calibration control circuitry adjusts a delay of the controllable delay circuit during calibration until the phase detection circuitry detects alignment. The calibration control circuitry controls the controllable delay circuit to generate a delay to the clock signal in dependence upon the delay that generated the alignment detected during calibration.

Interface for controlling the phase alignment of clock signals for a recipient device

A memory controller and a method of calibrating the memory controller are provided. Input circuitry in the memory controller receives a differential pair of data strobe signals from a memory and generates a logical data strobe signal in dependence on a voltage difference between the differential pair of data strobe signals. Hysteresis circuitry, when active, increases by a predetermined offset a threshold voltage difference at which the input circuitry changes a logical state of the logical data strobe signal. Gate signal generation circuitry generates a data strobe gating signal, wherein the memory controller interprets the logical data strobe signal as valid when the data strobe gating signal is asserted. The memory controller performs a training process to determine a timing offset for the data strobe gating signal with respect to said logical data strobe signal, wherein the training process provides a first phase in which the hysteresis circuitry is active and a second phase in which the hysteresis circuitry is inactive.

Memory controller using a data strobe signal and method of calibrating data strobe signal in a memory controller

A memory controller transmits a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A mask signal training procedure is carried out comprising three steps. Writing first and second values to the memory for a predetermined plurality of transitions of the data strobe signal with the mask signal set to indicate that the first data signal is valid and the second data signal is valid except for a selected transition of the predetermined plurality. Reading from the memory for the predetermined plurality of transitions of the data strobe signal. Determining a timing offset for the mask signal for which the value read at the selected transition matches the first value.

Memory controller and method of calibrating a memory controller

A method of calibrating a data signal receiver configured to receive a multi-bit data signal and an associated data strobe signal, wherein transitions of the data strobe signal indicate sample points for the multi-bit data signal. The method comprises the steps of: receiving, on each bit of the multi-bit data signal, a sample of a predetermined data pattern; determining, for each bit of the multi-bit data signal, a relative start timing value indicative of a start of the predetermined data pattern; determining, for each bit of the multi-bit data signal, a relative end timing value indicative of an end of the predetermined data pattern; determining, for each bit of the multi-bit data signal, a mid-point timing value halfway between the relative start timing value and the relative end timing value; applying a bit timing delay to each bit of the multi-bit data signal such that the mid-point timing values are aligned; and applying a strobe timing delay to the associated data strobe signal to align the associated data strobe signal with the aligned mid-point timing values.

Data signal receiver and method of calibrating a data signal receiver

A method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory, and a corresponding memory system are provided. The method comprising the steps of: putting the memory into a write levelling mode; incrementing an alignment delay applied to the data strobe signal until a transition point occurs at which a response of the memory to issuance of the data strobe signal transitions to an inverse state; performing an oversampling of the response of the memory over a selected interval following said transition point; repeating the steps of incrementing and performing an oversampling until, for a selected alignment delay, a majority of results of the oversampling is in the inverse state; performing a cycle alignment detection procedure to determine an identified clock cycle of a plurality of adjacent cycles of the clock signal, the identified clock cycle responsible for the transition point; and applying the selected alignment delay to the data strobe signal and applying a clock cycle selection to a data path in the system to match the identified clock cycle.

Method and apparatus for aligning a clock signal and a data strobe signal in a memory system

A calibratable delay chain having a delay chain and an adjustment circuitry varying a delay of each of the plurality of delay stages in the chain. The calibration circuitry is configured to calibrate a delay of the delay chain. The calibration circuitry includes calibration control circuitry for controlling the calibration and supplying the input value to an adjustment circuitry. Output selection circuitry is provided to select an output from a predetermined point along the delay chain. A bypass path bypasses the delay chain and a digital comparator compares an output from the delay chain and an output from the bypass path. An analogue comparator compares an output from the delay chain and an output from the bypass path. The calibration control circuitry is configured to control the output selection circuitry to output a signal from one point on the delay chain to the digital comparator.

Calibration of delay chains

An integrated circuitincludes a receiver circuitfor receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitrycouples an inputto a first node. Buffer circuitryis coupled between the first nodeand an outputcarrying the output signal Out. The conduction path circuitry comprises a first PMOS transistorand a second PMOS transistorconnected between the inputand the first node. A first NMOS transistoris connected between the inputand the first node. The gate of the second PMOS transistoris coupled to the outputto directly receive the output signal and thereby achieve rapid cut off of the charging of the nodewhen the input voltage rises beyond a certain level which switches the buffer circuitry

Receiver circuit with high input voltage protection

Calibration circuitryfor an off-chip driver circuitand/or an on-die termination circuitis provided using a parallel network of main transistors controlled by a N-bit calibration value. During the calibration operation, the N-bit calibration value is varied until a threshold impedance value is crossed by the combination of the main transistors. A rounding transistoris then used to determine which of the N-bit calibration values produces a combined impedance closest to the designed threshold impedance.

Reduced quantization error I/O resistor calibrator

An interface between first and second voltage domains is provided. A level shifter is configured to receive an input signal from the first voltage domain and to level shift the input signal to provide an output signal for passing to the second voltage domain. A control signal generator is configured to generate a second voltage domain control signal in dependence on at least one first voltage domain control signal from a controller in the first voltage domain. The level shifter is configured to be in a retention state when the second voltage domain control signal has a first value, such that its output signal is held constant even when the controller becomes not actively driven by the first voltage supply. The level shifter is configured to be in a transmission state when the second voltage domain control signal has a second value, wherein the output signal depends on the input signal.

Apparatus and method providing an interface between a first voltage domain and a second voltage domain

A power supply cell for distributing power supplied from a first voltage supply to an integrated circuit is disclosed. The power supply cell comprises: a layer comprising conductive material, the conductive material providing a conduction path for current flowing from the first voltage supply to a portion of the integrated circuit to be powered and further providing a protection path for surge current flowing between the first voltage supply and an electrostatic discharge protection device and between the electrostatic discharge protection device and the second voltage supply; the conductive material forming a first conduction path for providing a path for current flowing between the first voltage supply and the portion of the integrated circuit to be powered and for providing a portion of the protection path for surge current flowing between the first voltage supply and the electrostatic discharge protection device and a second conduction path for providing a further portion of the protection path for surge current flowing between the second voltage supply and the electrostatic discharge protection device; wherein the conductive material is arranged such that the first conduction path has a significantly lower resistance than the second conduction path.

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Bengaluru, India

Nidhir Kumar