International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Adeia Semiconductor Solutions LLC

Tessera LLC

Nicole A Saulnier

Lawrence Alfred Clevenger

Sivananda K Kanakasabapathy

Christopher J Penny

Sean David Burns

Roger Allan Quon

Injo Ok

Matthew Earl Colburn

Nelson M Felix

Yann A M Mignot

Kevin W Brew

Fee Li Lie

Gauri V Karve

Indira P Seshadri

Leigh Anne H Clevenger

Iqbal Rashid Saraf

Mona Abdulkhaleg Ebrish

Isabel Cristina Chu

Ekmini Anuja De Silva

Andrew Herbert Simon

John Ryan Sporre

Muthumanickam Sankarapandian

Deepika Priyadarshini

Jeffrey C Shearer

Timothy Mathew Philip

Siva Kanakasabapathy

Carl John Radens

John H Zhang

Balasubramanian Pranatharthiharan

Ruqiang Bao

Andrew Mark Greene

Hosadurga K Shobha

Terry Allen Spooner

Matthew Joseph BrightSky

Yiheng Xu

Myung-Hee Na

Steven Michael McDermott

Michael Rizzolo

Benjamin David Briggs

Zhenxing Bi

Sanjay C Mehta

Robert L Bruce

Karen Elizabeth Petrillo

Bartlet H Deprospo

Jin Ping Han

Hao Tang

Akil Khamisi Sutton

Prasad Bhosale

Richard Stephen Wise

Anuja E DeSilva

Takashi Ando

Vijay Narayanan

Soon-Cheon Seo

Praneet Adusumilli

Richard Stephan Wise

Hiroyuki Miyazoe

Paul Charles Jamison

Dexin Kong

Youngseok Kim

Derren Neylon Dunn

Adra Carr

Ravi K Bonam

Hari Prasad Amanapu

Michael M Crouse

Hyung Joo Shin

Sean D Burns

John R Sporre

Andrew M Greene

Matthew E Colburn

Roger A Quon

Jeffrey Shearer

Steven M Mcdermott

Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

FinFET gate cut after dummy gate removal

A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Self aligned pattern formation post spacer etchback in tight pitch configurations

A phase change memory bridge cell comprising a dielectric layer located on top of a at least one electrode, wherein a trench is located in the dielectric layer. A first liner located at the bottom of the trench in the dielectric layer and the first liner is located on the sidewalls of the dielectric layer that forms the sidewalls of the trench. A phase change memory material located on top of the first liner, wherein a top surface of the phase change memory material is aligned with a top surface of the dielectric layer, wherein the dielectric layer is located adjacent to and surrounding the vertical sidewalls of the phase change memory material, wherein a top surface of the phase change memory material is flush with a top surface of the dielectric layer.

Confined bridge cell phase change memory

Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

BEOL fat wire level ground rule compatible embedded artificial intelligence integration

A phase change memory (PCM) cell includes an electrode, a heater electrically connected to the electrode, a PCM material electrically connected to the heater, a second electrode electrically connected to the PCM material, an electrical insulator surrounding the PCM material, and a shield positioned between the PCM material and the electrical insulator, the shield comprising a reactive-ion-etching-resistant material.

Phase change memory cell spacer

A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Multi-layer phase change memory device

A method for forming a phase-change memory cell includes depositing a metal layer over a wafer such that the metal layer covers connection structures of the wafer. The method further includes removing a portion of the metal layer such that the connection structures of the wafer remain covered by a remaining portion of the metal layer. The method further includes forming a phase-change memory stack on a stack area of the remaining portion of the metal layer. The method further includes removing the remaining portion of the metal layer except in the stack area.

Phase change memory cell galvanic corrosion prevention

A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.

Self-aligned pattern formation for a semiconductor device

A semiconductor structure may include a heater surrounded by a second dielectric layer, a projection liner on top of the second dielectric layer, and a phase change material layer above the projection liner. A top surface of the projection liner may be substantially flush with a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Phase change memory cell with a projection liner

A mushroom type phase change memory (PCM) cell includes a projection liner located between a PCM volume and a bottom electrode. The projection liner has been retained from a layer previously utilized as an etch stop layer during the fabrication of PCM cell and/or the fabrication of the higher level IC device. The projection liner may extend beyond the PCM sidewall(s) or side boundary. This section of the projection liner may be located or buried under a dielectric or an encapsulation spacer and may increase thickness uniformity of the projection liner below the PCM volume.

Integrated phase change memory cell projection liner and etch stop layer

A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner

A method of forming a phase change memory device is provided. The method includes forming a spacer layer on a substrate, and forming a heater terminal contact in the spacer layer. The method further includes forming a liner layer on the heater terminal contact and the spacer layer, and forming a heater terminal in electrical contact with the heater terminal contact in the liner layer. The method further includes forming a conductive projection segment on the heater terminal. The method further includes forming a phase change material layer on the conductive projection segment, and forming a phase change material terminal on the phase change material layer, wherein an electrical current can pass between the heater terminal and the phase change material terminal through the phase change material layer.

Projected phase change memory devices

A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.

Phase change memory device

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Albany, NY, United States of America

Nicole A Saulnier