Apple Inc.

Nicolas Xavier Pena

Terence M Potter

Andrew M Havlir

Liang-Kai Wang

Yu P Sun

Christopher A Burns

Adrian J Isles

Mark H Nodine

Nathan Francis Sheeley

Irfan Waheed

Xiao-Long Wu

Patrick Peters

Techniques are disclosed relating to floating-point operations with down-conversion. In some embodiments, a floating-point unit is configured to perform fused multiply-addition operations based on first and second different instruction types. In some embodiments, the first instruction type specifies result in the first floating-point format and the second instruction type specifies fused multiply addition of input operands in the first floating-point format to generate a result in a second, lower-precision floating-point format. For example, the first format may be a 32-bit format and the second format may be a 16-bit format. In some embodiments, the floating-point unit includes rounding circuitry, exponent circuitry, and/or increment circuitry configured to generate signals for the second instruction type in the same pipeline stage as for the first instruction type. In some embodiments, disclosed techniques may reduce the number of pipeline stages included in the floating-point circuitry.

Floating-point multiply-add with down-conversion

This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled. The semiconductor design is partitionedand associated input constraints. The edits are further groupedand ordered. The invention also discovers a set of dependencies of the logic editsand checks that the ordering of groups obeys the dependencies. Each group of edits is further submitted to formal verificationand any input constraints assumed for any partitions are verified in their enclosing partition. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints

Method for piecewise hierarchical sequential verification

Growing community of inventors

Austin, TX, United States of America

Nicolas Xavier Pena