Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Renault

Renault S.a.s.

Nicolas Ventroux

Michel Harrand

Vincent David

Renaud Sirdey

Thierry Collette

Raphaël David

Tanguy Sassolas

Jean-Marc Philippe

Alexandre Carbon

Stéphane Louise

Olivier Heron

Frédéric Blanc

Stéphane Chevobbe

Laurent Le Garff

Marc Shapiro

Julien Peeters

David Vincent

Julien Guilhemsang

Robert Faure

Laurent Forgeot

Jean-Yves Stineau

Joël Cathebras

Tushar Gupta

The electronic architecture carries out the management of the functions of a vehicle, the functions being implemented via a set of sensors and actuators, the architecture comprising at least: a central computer; a real-time communication network; a set of interface modules, each module: aggregating signals from at least one of the sensors and sending the signals to the central computer via the communication network; and/or distributing control signals to at least one of the actuators; the central computer driving the actuators according to the signals from the sensors, the control signals for the actuators being sent to the interface modules via the communication network.

Electronic architecture for onboard system

An electronic system-level parallel simulation method by means of a multi-core computer system, comprising the parallel evaluation of a plurality of concurrent processes of the simulation on a plurality of cores of the computer system and comprising a sub-method of detection of conflicts of access to a shared memory of a simulated electronic system, the sub-method being implemented by a simulation kernel executed by the computer system and comprises: a step of construction of an oriented graph representative of access to the shared memory by the processes evaluated by the concurrent processes; and a step of detection of loops in the graph; a loop being considered representative of a conflict of access to the shared memory. A computer program product for implementing such a method is provided.

Electronic system level parallel simulation method with detection of conflicts of access to a shared memory

A method of performing Electronic System Level simulation using a multi-core computing system comprises the steps of: A) Running a Discrete Event Simulation kernel on a core of the multi-core computing system, within a dedicated OS-kernel-level thread; B) Using the Discrete Event Simulation kernel for generating a plurality of OS-kernel-level threads, each associated to a respective core, and for distributing concurrent processes of the simulation among them; C) Carrying out parallel evaluation of the concurrent processes within the corresponding threads using respective cores; and then D) Using the Discrete Event Simulation kernel for processing event notifications, updating a simulation time and scheduling next processes to be evaluated; steps C) and D) being carried out iteratively until the end of the simulation. A computer program product including a hardware description Application Program Interface and a Discrete Event Simulation kernel adapted for carrying out such a method is also provided.

Computer-implemented method of performing parallelized electronic-system level simulations

A distributed computation system comprising computation units and memory shared between computation units, comprises a hardware module for detecting conflicts of access of computation units to shared memory; each hardware module for detecting conflicts configured to: store a probabilistic data structure, indicative of the addresses of shared memory involved in the current transactions; receive at least one message indicative of request for access, by one computation unit to an address of shared memory; determine, from a probabilistic data structure, whether the address is already involved in a current transaction, and transmit a message indicating presence or absence of access conflicts; receive a message indicative or confirmative of reservation or releasing of an address of shared memory, and update the probabilistic data structure for the reserved addresses and the released addresses to be considered, as being/not being involved in a current transaction. A method for using the system is provided.

Distributing computing system implementing a non-speculative hardware transactional memory and a method for using same for distributed computing

A device is provided for accelerating, on a platform comprising a plurality of processing units, the execution of a SystemC simulation of a system, said simulation comprising a SystemC kernel and SystemC processes. The device comprises hardware means for scheduling the SystemC processes on the processing units in a dynamic manner during the execution of the simulation, these means making it possible notably to preempt the processing units.

Hardware device for accelerating the execution of a systemC simulation in a dynamic manner during the simulation

A system including a plurality of processing units for executing tasks in parallel and a communication network. The processing units are organized into clusters of units, each cluster comprising a local memory. The system includes means for statically allocating tasks to each cluster of units, so that a task of an application is processed by the same cluster of units from one execution to another. Each cluster includes cluster management means for allocating tasks to each of its processing units and space in the local memory for executing them, so that a given task of an application may not be processed by the same processing unit from one execution to another. The cluster management means includes means for managing the tasks, means for managing the processing units, means for managing the local memory and means for managing the communications involving its processing units. The management means operate simultaneously and cooperatively.

Statically allocating set of tasks to particular cluster and dynamically allocating each task to different processing units within cluster

In a device for managing data buffers in a memory space distributed over a plurality of memory elements, the memory space is allocatable by memory pages, each buffer including one or more memory pages. The buffers are usable by at least one processing unit for the execution of an application, the application being executed by a plurality of processing units executing tasks in parallel. The memory elements are accessible in parallel by the processing units. The device includes means for allocating buffers to the tasks during the execution of the application and means for managing access rights to the buffers. The means for managing the access rights to the buffers include means for managing access rights to the pages in a given buffer, to verify that writing to a given page does not modify data currently being read from the page or that reading from a given page does not access data currently being written to the page, in such a way as to share the buffer between unsynchronized tasks.

Device for managing data buffers in a memory space divided into a plurality of memory elements

The system for conducting intensive multitask and multistream calculation in real time comprises a central processor core (SPP) for supporting the system software and comprising a control unit (ESCU) for assigning threads of an application, the non-critical threads being run by the central processor core (SPP), whereas the intensive or specialized threads are assigned to an auxiliary processing part (APP) comprising a set of N auxiliary calculation units (APU, . . . , APUN-) that are optimized for fast processing of certain operations, a memory space (SMS) shared by the auxiliary calculation units (APU, . . . , APUN-) via an internal network and a unit (ACU) for controlling and assigning the auxiliary resources. The various elements of the system are arranged in such a manner that communication between the various auxiliary calculation units (APU, . . . , APUN-) or between those auxiliary calculation units (APU, . . . , APUN-) and the central processor core (SPP) is effected via the shared memory space (SMS) and the internal network.

Method and system for conducting intensive multitask and multiflow calculation in real-time

The invention relates to a method for scheduling the processing of tasks and to the associated device, the processing of a task comprising a step for configuring resources required for executing the task and a step for executing the task on the thereby configured resources, the method comprising a selection () of at least one level of independent tasks to be processed in accordance with an order of precedence and a step for sorting () out the tasks of the level of tasks to be processed in order to define, an order of priority in the processing of the tasks, depending on the number of resources required for processing the tasks on the one hand and on a time characteristic of the tasks on the other hand.

Method for configuring resources and scheduling task processing with an order of precedence

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Bures sur Yvette, France

Nicolas Ventroux