Texas Instruments Corporation

Nicolas Salamina

Marco Corsi

Roy Alan Hastings

Gabriel A Rincon

Michael R Kay

Gabriel Alfonso Ricon-Mora

Robert B Borden

Jeffrey W Sanders

An improved low-dropout ('LDO') voltage regulator incorporates a transient response boost circuit which is added to the slew-rate limited node at the control terminal of the LDO voltage regulator output transistor and provides improved transient response performance to the application of various load current step stimuli while requiring no standby or quiescent current during zero output current load conditions. The transient boost circuit supplies current to the slew-rate limited node only upon demand and may be constructed as either a localized positive feedback loop or a number of switching devices which conduct current only during slew-rate conditions.

Low-dropout voltage regulator incorporating a current efficient

A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages. The circuit can tolerate negative voltages up to approximately two diode drops on its output and gate drive terminals because (a) when transistor Q2 is conducting it is effectively configured as an NPN diode and the collector cannot sustain a voltage less than one base-emitter drop above its emitter, (b) transistor M13 is a DMOS transistor which can withstand negative voltages upon its source when it is nonconducting due to the interposition of the backgate between the source and the drain and (c) transistors M17 and M18 are returned to ground and not to the output terminal.

High speed biCMOS gate power for power MOSFETs incorporating improved

High speed biCMOS gate driver for MOSFETs incorporating improved

A voltage regulator circuit includes: a first MOS transistor 12 coupled between a voltage supply line and an output node 44, the first MOS transistor 12 providing a stable voltage on the output node 44; a source follower 24 coupled to a gate of the first MOS transistor 12; an amplifier 38 coupled to a gate of the source follower 24 for controlling the response of the first MOS transistor 12; negative feedback circuitry coupled between the output node 44 and the amplifier 38, the feedback circuitry providing feedback to the amplifier 38; a current conveyer 46 coupled to the first MOS transistor 12; and positive feedback circuitry 26 coupled between the current conveyer 46 and the source follower 24.

Low drop-out voltage regulator with PMOS pass element

A voltage regulator circuit (10) is provided. Regulator circuit (10) includes an amplifier (18) with an emitter follower output stage (26). Emitter follower stage (26) is coupled to a gate of a PMOS transistor (28). The source of transistor (28) is coupled to an input voltage at a power supply rail (12). Regulator (10) provides an output at node (14) at a drain of transistor (28). The output at node (14) is divided by resistors (30 and 34) and provided in a negative feedback loop to an input of amplifier (18). A reference voltage (22) is also provided to a second input of amplifier (18) such that the output at node (14) is a regulated voltage.

Circuit and method for regulating a voltage

A low power, break before make output circuit includes an output transistor pair 12 and 14, a first control circuit 20, a second control circuit 22, a first comparator 16, and a second comparator 18. First control circuit 20 has a first input coupled to a first digital control input and an output coupled to a control terminal of a first transistor 12 in the output transistor pair. Second control circuit 22 has a first input coupled to a second digital control input and an output coupled to a control terminal of a second transistor 14 in the output transistor pair. First comparator 16 has an input connected to the output of first control circuit 20 and an output connected to the second input of second control circuit 22. First comparator 16 compares a voltage at the control terminal of first transistor 12 to a first predetermined voltage and formulates a voltage at its output in response to the comparison. Second comparator 18 has an input connected to the output of second control circuit 22 and an output connected to the second input of first control circuit 20. Second comparator 18 compares a voltage at the control terminal of second transistor 14 to a second predetermined voltage and formulates a voltage at its output in response to the comparison. The voltages at the output of first comparator 16 and second comparator 18 influence the outputs of first control circuit 20 and second control circuit 22 thereby ensuring that first transistor 12 is not conducting when second transistor 14 is activated.

Comparator circuit for decreasing shoot-through current on power switches

An amplifier circuit (10) is provided. The amplifier (10) includes an amplifier stage (14) coupled to an output stage (18). Output stage (18) comprises a sourcing circuit (20) and a sinking circuit (22). The current in sinking circuit (22) is approximately mirrored at low current in mirror circuit (34). At higher currents, resistor (36) maintains the current in mirror circuit (34) below the current in sinking circuit (22). A diode (38) diverts current to mirror circuit (34) to aid sinking circuit (22) in sinking current from a load (12). A current source (29) supplies current to sourcing circuit (20) and mirror circuit (34). A control signal output by amplifier stage (14) causes mirror circuit (34) to draw or not draw current from current source (29). If mirror circuit (34) draws current from current source (29), output stage (18) sinks current in sinking circuit (22). If mirror circuit (34) does not draw current from current source (29), output stage (18) sources current through sourcing circuit (20).

Controlled current output stage amplifier circuit and method

An amplifier circuit (10) is provided. Amplifier (10) has an amplifier stage (14) that is coupled to control an output stage (18). Output stage (18) includes a sourcing circuit (20) and a sinking circuit (22). Output stage (18) also includes a mirror circuit (42) that is coupled to an output of amplifier stage (14). Output stage (18) also includes a current balancing circuit (30) coupled to mirroring circuit (42) and sourcing circuit (20). Mirroring circuit (42) draws current from balancing circuit (30) in response to a first predetermined output from amplifier stage (14) such that balancing circuit (30) causes an insignificant current to flow in sourcing circuit (20). Thus amplifier (10) operates to sink current from an external load (12). Alternatively, mirroring circuit (42) may draw an insignificant current from balancing circuit (30) in response to a second predetermined output of the amplifier stage (14). This causes a significant current flow in sourcing circuit (20).

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Sachse, TX, United States of America

Nicolas Salamina