Allegro Microsystems, LLC

Nicolás Rafael Biberidis

Nicolas Rigoni

Octavio H Alpago

Hernán D Romero

Gerardo A Monreal

Sundar Chetlur

Harianto Wong

Lucas Intile

James McClay

Leandro Tozzi

Vyankatesh Gupta

Fernando Orge

Ahmed Hassan Fahmy

Muhammed Sarwar

A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.

Method and apparatus for eliminating bit disturbance errors in non-volatile memory devices

A method is disclosed for use in an electronic device having a non-volatile storage device and a volatile storage device, the method comprising: retrieving a first encoded data packet from a first address in the non-volatile storage device; decoding the first encoded data packet to obtain a first data item and a first error code corresponding to the first data item, the first encoded data packet being decoded by using a first coding key that is associated with the first address; detecting whether the first data item is corrupt based on the first error code and an error correction function, storing the first data item at a first address in the volatile storage device when the first data item is not corrupt, and transitioning the electronic device into a safe state when the first data item is corrupt.

Non-volatile memory data and address encoding for safety coverage

In one aspect, an integrated circuit (IC) includes a multiplexor configured to receive data from a non-volatile memory and configured to receive data from a shadow memory, a shift register configured to generate a first signature from the data received from the non-volatile memory and configured to generate a second signature from the data received from the shadow memory; a signature storage configured to store the first signature; and a shadow memory checking controller configured to enable the multiplexor to send the data from the non-volatile memory to the shift register, and send a command to reload the shadow memory with data from the non-volatile memory in response to receiving an error flag. The IC also includes a comparator circuit configured to compare the first signature and the second signature and configured to send the error flag in response to the first signature and the second signature being different.

Shadow memory checking

A magnetic field sensor includes a first magnetic field sensing element first generating a first signal having a first axis of maximum sensitivity, a second magnetic field sensing element for generating a second signal and having a second axis of maximum sensitivity, one or more detectors for receiving an output of the first magnetic field sensing element or the second magnetic field sensing element, and a processor that receives an output of the one or more detectors and uses the output of the one or more detectors to calculate a first constant Kand a second constant Kand then uses Kand Kto compensate for an orthogonality error between the first axis of maximum sensitivity and second axis of maximum sensitivity. The detectors include peak detectors and/or zero-crossing detectors that compare the output of the first input signal or the second input signal with a threshold or zero.

Non-orthogonality compensation of a magnetic field sensor

A method for multi-level memory safety for a sensor integrated circuit can include loading a blocking bit into a volatile memory from a non-volatile memory and providing the blocking bit to a gating circuit from the volatile memory. Further, the method may include the gating circuit determining whether to provide a default value to a functional logic based upon the provided blocking bit.

Multi-level memory safety of a sensor integrated circuit

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Barcelona, Spain

Nicolás Rafael Biberidis