Inside Technologies

Nicolas Pangaud

Bruno Charrat

Eric Bouyoux

Sean Commercial

The present invention relates to a pipeline microprocessor (MP) comprising a first pipeline stage (ST ) comprising means IPC, MMU, PC, B DEC ) for reading and decoding instructions (CODE , ADRs, ADRd) of a program recorded in a memory (MEM), and a second pipeline stage (ST ), contiguous to the first pipeline stage, comprising two sectors (ST , ST ) activated one after the other during complementary half-cycles of a clock signal (H ) of the microprocessor. The first sector reads data contained in two registers (Rd, Rs) of a bank of registers (BANK , BANK ) of the microprocessor and carries out an operation on the data according to an instruction (CODE , ADRs, ADRd) received at the previous clock cycle. The second sector (ST ) comprises means (B DEC ) to record the result of the operation in a register of the bank of registers (BANK BANK ). Application especially to chip cards.

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Aix en Provence, France

Nicolas Pangaud