National Semiconductor Corporation

Nicolas Nodenot

Laurence Douglas Lewicki

Amit Rane

Yongseon Koh

Benjamin Clyde Buchanan

Amjad T Obeidat

Circuitry for adaptive signal equalizing with coarse and fine boost controls by providing multiple serially coupled stages of parallel controllable DC and AC signal gains with coarse and fine gain controls provided across all stages.

Adaptive signal equalizer with segmented coarse and fine controls

Method and system for adaptive signal equalizing with alternating boost and amplitude controls. In accordance with one exemplary embodiment, data signal boost control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a higher frequency, while sliced data signal amplitude control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a lower frequency.

System and method for providing adaptively equalized data signal with alternately adjusted data signal boost and sliced data signal amplitude

System and method for adaptive signal equalizing in which overlapping data signal equalization paths provide cumulative data signal equalization to provide multiple equalized data signals having different available amounts of equalization. Signal slicing circuitry slices the equalized data signals to provide multiple sliced data signals, from which the sliced data signal selected as an output data signal is dependent upon the data rate of the incoming data signal.

System and method for adaptively equalizing data signals with higher and lower data rates

A system and a method are disclosed for providing a parameterized analog feedback loop for continuous time adaptive equalization that incorporates low frequency attenuation gain compensation. N adaptive equalizer stages are coupled in series and a slicer circuit is coupled to the last (Nth) adaptive equalizer stage. A single equalizer adaptation control loop controls the frequency response of the adaptive equalizer stages to compensate for the attenuation of a lossy channel. The single equalizer adaptation control loop also compensates for the direct current (DC) loss in the lossy channel by modulating a bias current in the slicer circuit to scale the low frequency feedback with adaptation coefficients that correlate with channel length.

System and method for providing a parameterized analog feedback loop for continuous time adaptive equalization incorporating low frequency attenuation gain compensation

A system and method is disclosed for providing a clock and data recovery circuit with a fast bit error rate self test capability. A bit error rate test control unit is provided that causes the clock and data recovery circuit to sample data adjacent to an edge of a bit period to create errors at a relatively high bit error rate. This is accomplished by intentionally introducing an interpolator offset in a phase position of a data clock signal. The test control unit generates a first bit error rate and then subsequently generates a second bit error rate. The test control unit then uses the values of the first and second bit error rates to extrapolate a value of bit error rate for the clock and data recovery circuit that corresponds to a zero value of interpolator offset.

System and method for providing a clock and data recovery circuit with a fast bit error rate self test capability

A system and method is disclosed for providing a clock and data recovery circuit with a self test capability. A test control unit is provided that causes the clock and data recovery circuit to continuously alter a phase of an interpolated clock signal. A user selects a preselected bit pattern that causes the digital control circuitry of the clock and data recovery circuit to advance or retard the phase of the interpolated clock signal. The test control unit compares the advanced or retarded phase of the interpolated clock signal with a reference clock signal to determine a frequency difference between the two clock signals. The test control unit uses the frequency difference to determine the test status of the clock and data recovery circuit.

System and method for providing a clock and data recovery circuit with a self test capability

Power management for a computer system and device is accomplished by implementing two separate power modes in a serially-connected device, and selecting from the two power modes depending on the state of a receiver in the device. A signal detector within the receiver is connected to a serial interface port of the device to detect the presence of an input signal. A power controller selects a first power mode for the device when the signal detector detects the input signal and a second power mode for the device when the input signal is not detected by the signal detector.

Device and computer system for power management using serial link connections

A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the amplifier unit provide the data sampling comparator with a single ended clock signal that is relatively immune to power supply noise. The data sampling comparator samples an input data stream with minimal jitter due to power supply noise. The data sampling comparator consumes less static power than a current mode logic D flip flop and also has output levels that are compatible with complementary metal oxide semiconductor (CMOS) logic.

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Mountain View, CA, United States of America

Nicolas Nodenot