Infineon Technologies Ag

Qimonda Ag

Other

Kabushiki Kaisha Toshiba

International Business Machines Corporation

Infineon Ag

Qimonda Flash Gmbh

Nicolas Nagel

Rainer Bruchhaus

Andreas Hilliger

Thomas Mikolajick

Jingyu Lian

Uwe Wellhausen

Stefan Gernhardt

Josef Willer

Gerhard Beitel

Walter Hartner

Gerhard Enders

Dominik Olligs

Koji Yamakawa

Michael Lester Wise

Christoph Kleint

Bum-ki Moon

Matthias Kr&ouml;nke

Bum Ki Moon

Michael R&ouml;hner

Franz Hofmann

Keitaro Imai

Haoren Zhuang

Michael Specht

Jenny Lian

Chenting Lin

Karl Hornik

Igor Kasko

Matthias Markert

Takamichi Tsuchiya

Torsten Mueller

Ravikumar Ramachandran

Kwong Hon Wong

Hermann Wendt

Tohru Ozaki

Kazuhiro Tomioka

Christopher Carr Parks

Hiroshi Itokawa

Yoshinori Kumura

Dirk Manger

Volker Weinrich

Detlev Richter

Roman Knoefler

Ulrich Egger

Moto Yabuki

Jens-Uwe Sachse

Veronika Polei

Lars Bach

Bum-Ki Moon

Frank Heinrichsdorff

Matthias Krönke

Dirk Caspary

Martin Verhoeven

Steffen Meyer

Robert Primig

Hocine Boubekeur

Young Limb

Michael Röhner

Andreas Voerckel

Thomas Tatry

Patrick Haibach

Jing Yu Lian

Andre&aacute;s Hilliger

Gerhard Adolf Beitel

An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion.

Integrated circuit and method of forming an integrated circuit

A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.

Storage cell having a T-shaped gate electrode and method for manufacturing the same

A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

Memory cell arrangements

A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and annealed. The patterned layer structure is at least partially removed. Replacing material is formed in the region in which the patterned layer structure has been removed, thereby forming the at least one NAND-coupled semiconductor component.

Method of manufacturing at least one semiconductor component and memory cells

Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

Integrated circuit having NAND memory cell strings

Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.

Integrated circuits and methods of manufacturing thereof

A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiOand SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Hard mask layer stack and a method of patterning

The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays.

Integrated circuits, methods for manufacturing integrated circuits, integrated memory arrays

A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional 'contact to interconnect' structures.

Method for forming a semiconductor product and semiconductor product

An interconnection structure includes two staggered contact rows of evenly spaced contacts. Each contact row extends along a first direction. The interconnection structure further includes conductive lines extending along a second direction that intersects the first direction. The interconnection structure further includes intermediate contacts, where each intermediate contact is in contact with one of the contacts and one of the conductive lines.

Interconnection structure and method of manufacturing the same

A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.

Method of forming contacts using auxiliary structures

An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.

Self-aligned V0-contact for cell size reduction

A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric layer. The hard mask layer may be composed of a material that has an etch resistance as compared to the interlayer dielectric material, e.g., nitride. Openings in the hard mask define positions for the contacts to the local interconnects exposed in the top section.

Method of forming a contact in a flash memory device

An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.

Multi-layer electrode and method of forming the same

Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO) substrate in capacitor structures of memory devices.

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Growing community of inventors

Dresden, Germany

Nicolas Nagel