Intel Corporation

Nicolas L Irizarry

Balaji Srinivasan

Yasir Mohsin Husain

Jaydip Bharatkumar Patel

Ashraf B Islam

Noble Narku-Tetteh

Ripudaman Singh

Techniques for controlling current through memory cells is disclosed. In the illustrative embodiment, a fine-grained current source and a coarse-grained current source can both be activated to perform an operation on a phase-change memory cell. The coarse-grained current source is briefly activated to charge up the capacitance of an electrical path through the memory cell and then turned off. The fine-grained current source applies a current pulse to perform the operation on the memory cell, such as a reset operation. By charging up the electrical path quickly with the coarse-grained current source, the fine-grained current source can quickly perform the operation on the memory cell, reducing the thermal disturbance caused by the operation on nearby memory cells.

Technologies for controlling current through memory cells

A method, apparatus and system. The method includes: generating a feedback voltage Vin a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vat said one of the BL or WL; generating, in a reference circuit, one of a reference voltage Vto track a feedback voltage of the feedback circuit or a mirror current Ito track a current Ithrough said each of the memory cells; and providing one of values for both Vand V, or for an output voltage Vcorresponding to I, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of Vwith Vor based on V.

Apparatus, system and method to sense a logic state of a memory cell in a three-dimensional memory device

Embodiments of bus circuits and related techniques are disclosed herein. In some embodiments, a bus circuit may include: a source follower arrangement, including a first transistor and a second transistor, coupled between a supply voltage and an access line of a memory cell, wherein the first transistor and the second transistor each have a gate terminal and wherein the access line is a bit line or a word line; a capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to a reference voltage; and a switch coupled between the first terminal of the capacitor and a voltage regulator. Other embodiments may be disclosed and/or claimed.

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Folsom, CA, United States of America

Nicolas L Irizarry