Globalfoundries Inc.

International Business Machines Corporation

Applied Materials, Inc.

Stmicroelectronics (crolles 2) Sas

Stmicroelectronics S.a.

Globalfoundries U.S. Inc.

Applied Materials Israel Limited

Globalfoundries U.S. 2 LLC

Nicolas L Breil

Oleg Gluschenkov

Christian Lavoie

Ahmet Serkan Ozcan

Kathryn Turner Schonenberg

Alexander Reznicek

Veeraraghavan S Basker

Shogo Mochizuki

Emre Alptekin

Rishikesh Krishnan

Abhijit Basu Mallick

Keith Kwong Hon Wong

Herbert Lei Ho

Swaminathan T Srinivasan

Ricardo Alves Donaton

Dong Hun Kang

Brent A Anderson

Cyril Cabral, Jr

Michael Patrick Chudzik

Martin Michael Frank

Unoh Kwon

Siddarth A Krishnan

Claude Ortolland

Jian Yu

Domingo A Ferrer

Byeong Chan Lee

Praneet Adusumilli

Avgerinos V Gelatos

Benjamin Colombeau

Didier Dutartre

Dror Shemesh

Yves Campidelli

Manoj Vellaikal

Fredrick Fishburn

Neal A Makela

Olivier Gourhant

Vadim Kuchik

Lisa Mcgill

Pei Liu

Bocheng Cao

Jerome Bienacel

A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structures having an n-type metal oxide semiconductor (n-MOS) region and/or a p-type MOS (p-MOS) region, the cavity shaping process comprising forming an n-MOS cavity in an exposed surface of the n-MOS region and/or a p-MOS cavity in an exposed surface of the p-MOS region, wherein the cavity shaping process is configured to increase the surface area of the exposed surface of the n-MOS region or the p-MOS region. In some embodiments, the method includes performing a first selective deposition process to form a p-MOS cavity contact, selectively in the p-MOS cavity.

Electrical contact cavity structure and methods of forming the same

A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

Void-free contact trench fill in gate-all-around FET architecture

The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.

System and methods for dram contact formation

Methods for forming silicide films are disclosed. Methods of selectively depositing metal-containing films on silicon surfaces which are further processed to form silicide films are disclosed. Specific embodiments of the disclosure relate to the formation of silicide films on FinFET structures without the formation of a metal layer on the dielectric.

Silicide films through selective deposition

The disclosure provides for a transistor which may include: a gate stack on a substrate, the gate stack including a gate dielectric and a gate electrode over the gate dielectric; a channel within the substrate and under the gate stack; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion and the second coefficient of diffusion is less than the third coefficient of diffusion.

Transistor and method of forming same

Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.

Soi FinFET fins with recessed fins and epitaxy in source drain region

A method for detecting voids in a metal line of a semiconductor device die includes: scanning an electron beam upon a selected location on the die containing the metal line; determine gray levels in an image produced by collected electrons of the electron beam backscattered from the selected location on the die; and identifying one or more voids in the metal line based on differences between the gray levels in the image.

Method for detecting voids and an inspection system

An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.

Contacts to semiconductor substrate and methods of forming same

A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.

Modified tungsten silicon

Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed. The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.

Silicon germanium fins on insulator formed by lateral recrystallization

Voidless contact metal structures are provided. In one embodiment, a voidless contact metal structure is provided by first providing a first contact metal that contains a void within a contact opening. The void is then opened to provide a divot in the first contact metal. After forming a dielectric spacer atop a portion of first contact metal, a second contact metal is then formed that lacks any void. The second contact metal fills the entirety of the divot within the first contact metal. In another embodiment, two diffusion barrier structures are provided within a contact opening, followed by the formation of a contact metal structure that lacks any void.

Voidless contact metal structures

A first aspect of the invention provides for a transistor. The transistor may include a gate stack on a substrate; a channel under the gate stack within the substrate; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer substantially separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion.

SOI FinFET fins with recessed fins and epitaxy in source drain region

Growing community of inventors

Wappingers Falls, NY, United States of America

Nicolas L Breil