Arm Limited

Nicolas Jean Phillippe Huot

Gilles Eric Grandou

Melanie Emanuelle Lucie Teyssier

Simon John Craske

Florent Begon

Jocelyn Francois Orion Jaubert

Louis-Marie Vincent Mouton

Stephane Eric Sebastian Brochier

A data processing system () includes memory protection circuitry () storing access control data for controlling accesses to data at memory addresses within a main memory (). An access control cache () may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry () to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache () is storing access control data for a memory access request, then the access control data stored within the access control cache () is used in place of access control data retrieved form the memory protection circuitry (). In the first embodiment, access control data may be determined to be cachable is if is associated with a region of memory addresses within a plurality of hierarchically ordered memory addresses that is a highest order region which encompasses all the memory addresses within that region.

Provision of access control data within a data processing system

A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.

Apparatus and method for predicting target storage unit

A data processing apparatus includes a data processor, and a data store for storing a plurality of identifiers identifying a cache way in which a corresponding value from a set associative cache is stored. The plurality of identifiers corresponding to a plurality of values stored in consecutive addresses such that a data store stores identifiers for values stored in a region of said memory. Included is a current pointer store for pointing to a most recently accessed storage location in said data store and circuitry to determine an offset of an address of said cache access request to an immediately preceding cache access request. Lookup circuitry determines if said pointer is pointing to an address within said region and said data processor identifies said cache way from said stored identifier pointed to by said current pointer if it has a valid indicator associated therewith.

Cache accessing using a micro TAG

Growing community of inventors

Valbonne, France

Nicolas Jean Phillippe Huot