Agilent Technologies, Inc.

Hewlett-packard Company

Other

Philips Lumileds Lighting Company LLC

Nicolas J Moll

Sandeep Raj Bahl

Mark R Hueschen

Hans G Rohdin

Michael Ragan Krames

Daniel Bernardo Roitman

Phillip W Barth

Chung-Yi Su

Ying-Lan Chang

Stephen Andrew Stockman

Jennifer Lu

Dave P Bour

Gloria E Hofler

David Dutton

Thomas Edward Kopley

John Stephen Kofol

Christopher P Kocot

Yu-Min Houng

Fred A Kish

Nathan Frederick Gardner

Sung Soo Yi

Herman C Chui

Tun-Sein Tan

Colombo R Bolognesi

Arlene Sachiyo Wakita-Oyama

Marek E Mierzwinski

Synthetic nanopore fabrication methods and structures are provided. Nanoscale transistor fabrication methods and structures are provided.

Methods of fabrication employing nanoscale mandrels

The extraction efficiency of a light emitting device can be improved by making the absorbing device layers as thin as possible. The internal quantum efficiency decreases as the device layers become thinner. An optimal active layer thickness balances both effects. An AlGaInP LED includes a substrate and device layers including an AlGaInP lower confining layer of a first conductivity type, an AlGaInP active region of a second conductivity type, and an AlGaInP upper confining layer of a second conductivity type. The absorbance of the active region is at least one fifth of the total absorbance in the light-emitting device. The device optionally includes at least one set-back layers of AlGaInP interposing one of confining layer and active region. The p-type upper confining layer may be doped with oxygen improve the reliability.

lll-phosphide light emitting devices with thin active layers

Nanostructures and methods of making the same are described. In one aspect, a film including a vector polymer comprising a payload moiety is formed on a substrate. The film is patterned. Organic components of the patterned film are removed to form a payload-comprising nanoparticle.

Nanostructures and methods of making the same

A heterojunction bipolar transistor (HBT), comprises a collector formed over a substrate, a base formed over the collector, an emitter formed over the base, and a tunneling suppression layer between the collector and the base, the tunneling suppression layer fabricated from a material that is different from a material of the base and that has an electron affinity equal to or greater than an electron affinity of the material of the base.

Gallium arsenide antimonide (GaAsSB)/indium phosphide (InP) heterojunction bipolar transistor (HBT) having reduced tunneling probability

A method for planarizing a substrate surface having a non-planar surface topography comprises forming a material layer over the substrate, the material layer having a surface topography, determining the surface topography of the material layer, and forming a mask using information relating to the surface topography of the material layer. The mask defines portions of averaging regions of the material layer for selective removal to equalize the averaging regions in average height, the averaging regions having a maximum dimension. The material layer is etched using the mask, and a planarizing layer is formed over the substrate surface. The planarizing layer provides a low-pass lateral filtering effect characterized by a length greater than the maximum dimension of the averaging region. The mask is created by determining the localized height of the material layer across a surface and using the mask to etch away corresponding portions of the material layer so that the average surface of the material layer approximates a planar surface. The surface of the second material layer is substantially planar. The system and method for planarizing a material layer provides for forming a substantially planar layer of material over a non-planar topography.

System and method for planarizing a substrate surface having a non-planar surface topography

A heterojunction for a semiconductor device. The heterojunction has a first region formed from a first semiconductor material having a first conductivity type, a second region formed from a second semiconductor material having a second conductivity type, and an intermediate layer between the first region and the second region. The band line-up of the first region, the intermediate layer, and the second region has no bound states in its conduction band and no bound states in its valence band. The intermediate layer has a thickness small enough to allow electrons to tunnel from the first region to the second region with negligible attenuation. The semiconductor device may be a heterojunction bipolar transistor. The conduction band of the intermediate layer has a higher energy level than the conduction bands of the first and second regions.

Heterojunction semiconductor device having an intermediate layer for providing an improved junction

A heterojunction bipolar transistor (HBT), including an emitter formed from a first semiconductor material, a base formed from a second semiconductor material, and a grading structure between the emitter and the base is disclosed. The grading structure comprises a semiconductor material containing at least one element not present in the first and second semiconductor materials, where the grading structure has a conduction band energy substantially equal to a conduction band energy of the base at an interface between the base and the grading structure, and where the grading structure has a conduction band energy substantially equal to a conduction band energy of the emitter at an interface between the emitter and the grading structure.

Heterojunction bipolar transistor (HBT) having improved emitter-base grading structure

An HBT having an InP collector, a GaAsSb base and an InP emitter in which the base is constructed using a thin layer of GaAsSb. The thin base layer can be constructed of a GaAsSb material with a composition having a bulk lattice constant that matches the bulk lattice constant of the material of the collector. The thickness of the GaAsSb base layer is less than 49 nm, and preferably less that about 20 nm. Alternatively, the thin base layer is of a GaAsSb composition that includes a higher As content, resulting in a low conduction band energy discontinuity at the emitter-base junction. Such a GaAsSb base layer has a lattice constant that conforms to the lattice constant of the collector because it is thinly grown so as to be pseudomorphically &ldquo;strained&rdquo; over the collector. A high base doping level is used to reduce the sheet resistivity and lower the base series resistance that results from the thinly grown base layer.

Thin gallium-arsenide-antimonide base heterojunction bipolar transistor (HBT) having improved gain

A heterojunction bipolar transistor (HBT) having a base-emitter junction that exhibits the desirable properties of a GaAsSb/AlInAs interface, but which includes an intermediate layer in the emitter such that the intermediate layer contacts the GaAsSb base and the AlInAs emitter. The intermediate layer is sufficiently thin to be substantially electrically transparent, but sufficiently thick to provide a surface over which to grow the AlInAs emitter. The intermediate layer may be of a material such as InP, which has a bulk lattice constant that matches the lattice constant of the GaAsSb base and the AlInAs emitter. Alternatively, the intermediate layer may be of a material having a lattice constant different than that of the GaAsSb base and the AlInAs emitter, but may be pseudomorphically grown so as to provide an apparent lattice-match to the GaAsSb base and the AlInAs emitter.

Heterojunction bipolar transistor (HBT) having an improved emitter-base junction

A transistor structure with a degradation-stop layer that prevents degradation of underlying semiconductor layers while minimizing any increase in the gate leakage current is disclosed. In one embodiment, a transistor structure includes: a substrate; a channel layer formed of a charge transport material over the substrate; a Schottky barrier layer formed of an aluminum-containing material over the channel layer; a degradation-stop layer formed of a substantially aluminum-free material over the Schottky barrier layer; and a source, a drain and a gate. The source and the drain being formed over or alloyed through the degradation-stop layer, and a lower portion of the gate extends down through an exposed portion of the degradation-stop layer and is in physical and electrical contact with the Schottky barrier layer.

Sintered gate schottky barrier fet passivated by a degradation-stop layer

A semiconductor diode for providing a reduced recovery time at room temperature independent of any minority carrier recombination. The diode of the present invention comprises a first semiconductor material having a type of majority carriers and having a sub-band ordering associated with the majority carriers. The diode further comprises a second semiconductor material contacting the first material at a heterojunction, the second semiconductor material having the same type of majority carriers as the first semiconductor material and having a sub-band ordering associated with the majority carriers that is different from that of the first semiconductor material. It is theorized that the semiconductor diode of the present invention has a recovery time dependent upon scattering of carriers to various energy sub-bands within a heterojunction of the two different semiconductor materials. The diode of the present invention provides a reduced recovery time since a time of such scattering is extremely short.

Unipolar band minima devices

A room temperature high speed transistor that does not suffer deleterious effects from plasmon scattering. The transistor of the present invention comprises a semiconducting base region having a type of majority carriers and sub-band ordering associated with the majority carriers. The transistor further comprises a semiconducting collector region contacting the base region at a collector-base heterojunction, the semiconducting collector region having the same type of majority carriers as the semiconducting base region and having a sub-band ordering different than that of the base region. The transistor further comprises a semiconducting emitter region contacting the base region at an emitter-base heterojunction, the semiconducting emitter region having the same type of majority carriers as the semiconducting base region. In active operation of the transistor of the present invention, carriers are injected from a main sub-band in the emitter region into a satellite sub-band the base region. The carriers are then transported from the satellite sub-band in the base region to a main sub-band in the collector region. Intravalley scattering processes, including plasmon scattering, are not deleterious in the present invention because the carriers injected into satellite sub-band of the base region are successful collected in the main sub-band of the collector region independent of any energy lost through the intravalley scattering.

Band minima transistor

A charge injection transistor is a real-space electron transfer heterostructure with several novel features. The channel layer is comprised of In.sub.0.25 Ga.sub.0.75 As supported by a buffer layer of Al.sub.0.3 Ga.sub.0.7 As resting on the substrate. A barrier layer comprised of Al.sub.0.1 Ga.sub.0.9 As overlays the channel layer. Over this barrier is a layer of GaAs forming the electron drift region. The collector electrode is located on top of this drift layer, between the source and heater electrodes, which extend downward through the drift and barrier layers and create the electric field in the channel layer. Positive voltages are applied to the heater and collector, relative to the source. Electrons flow through the channel region and become heated. At sufficiently high temperature they escape over the barrier and travel through the drift region to the collector. In comparison with previous devices, the use of InGaAs in the channel layer provides a deeper quantum well for the conduction electrons, and suppresses leakage through the barrier at room temperatures. The collector drift layer has a short transit time delay. The location of the collector reduces parasitic leakage from the source, and the collector capacitance is small. These features enhance the high frequency performance of the device. The limiting power gain frequency and current gain frequency are at least twice the corresponding values attained in previous devices.

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Woodside, CA, United States of America

Nicolas J Moll