International Business Machines Corporation

Stmicroelectronics Gmbh

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Globalfoundries Inc.

Bell Semiconductor, LLC

Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Nxp B.v.

Adeia Semiconductor Bonding Technologies Inc.

Renesas Electronics America Inc.

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Nicolas J Loubet

Kangguo Cheng

Qing Liu

Prasanna Khare

Ruilong Xie

Julien Frougier

Pierre Morin

Bruce Bennett Doris

Alexander Reznicek

Xin Miao

Junli Wang

Hong He

Michael A Guillorn

Tenko Yamashita

Shogo Mochizuki

Shay Reboh

Shom Ponoth

Veeraraghavan S Basker

Pietro Montanini

Balasubramanian Pranatharthiharan

Daniel Chanemougame

Zhenxing Bi

Su Chen Fan

Maud Vinet

Huimei Zhou

Emmanuel Augendre

Peng Xu

Jingyun Zhang

Yann Mignot

Ali Khakifirooz

Chanro Park

Chun-chen Yeh

Ajey Poovannummoottil Jacob

Wenyu Xu

Steven J Bentley

Muthumanickam Sankarapandian

Didier Dutartre

Lawrence Alfred Clevenger

Isaac Lauer

Ruqiang Bao

Andrew Mark Greene

Sanjay C Mehta

Huiming Bu

Indira P Seshadri

Devendra K Sadana

Stephen W Bedell

Chen Zhang

Dechao Guo

Hemanth Jagannathan

Terence B Hook

Ekmini Anuja De Silva

Scott D Luning

Richard Anthony Conti

James J Demarest

Stefan Schmitz

Edward J Nowak

Pouya Hashemi

Juntao Li

Choonghyun Lee

Theodorus E Standaert

Karthik Balakrishnan

Ramachandra Divakaruni

Vijay Narayanan

Fee Li Lie

Reinaldo Ariel Vega

Xiuyu Cai

Robert Russell Robison

Pranita Kulkarni

Joshua M Rubin

Balasubramanian S Haran

Nelson M Felix

Gauri V Karve

Donald Francis Canaperi

Cheng Chi

Laurent Grenouillet

Yi Qi

Leigh Anne H Clevenger

Stephane Monfray

Jing Guo

Kirsten Emilie Moselund

Effendi Leobandung

Carl John Radens

Oleg Gluschenkov

Christian Lavoie

Heng Wu

Min Gyu Sung

Amlan Majumdar

Ravikumar Ramachandran

Kisik Choi

Nicholas Anthony Lanzillo

Philippe Coronel

Nicolas Posseme

Chun Wing Yeung

Anthony I Chou

Rama Divakaruni

Jody Alan Fronheiser

Raghavasimhan Sreenivasan

Charan V Surisetty

Tao Li

Miaomiao Wang

An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes a source drain contact above and contacting a source drain region of a semiconductor device. The interconnect structure also includes a via above and contacting the source drain contact. The via includes a lower portion with an uppermost surface that contacts a lowermost surface of an interlayer dielectric.

Liner-less via contact

A CMOS (complementary metal-oxide semiconductor) device includes an n-channel metal-oxide semiconductor (NMOS) device, a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material, a first NMOS gate separated from a first PMOS gate by the second dielectric material, a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the NMOS gate and the PMOS gate, the metal link disposed above the second dielectric material, a first source/drain (S/D) contact disposed above the second dielectric material, the first S/D contact disposed in contact with both NMOS S/D region and a PMOS S/D region, and a second S/D contact disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a single S/D region.

Semiconductor device having hybrid middle of line contacts

A microelectronic structure including a bottom transistor having a gate region aligned along a first axis. An upper transistor located on top of the bottom transistor, where the upper transistor has a gate region that is aligned along a second axis, and where the second axis is perpendicular to the first axis.

SRAM with staggered stacked FET

Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.

Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors

A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

Method of making a semiconductor device using a dummy gate

A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

Stacked FETS including devices with thick gate oxide

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

Gate-cut and separation techniques for enabling independent gate control of stacked transistors

A semiconductor structure may include one or more nanosheet field-effect transistors formed on a first portion of a substrate, and one or more fin field-effect transistors formed on a second portion of the substrate. A source drain of the one or more nanosheet field-effect transistors or a gate of the one or more nanosheet field-effect transistors may be separated from the substrate by an isolation layer. A source drain of the one or more fin field-effect transistors or a gate of the one or more fin field-effect transistors may be in direct contact with the substrate. The semiconductor structure may include a gate spacer surrounding the gate of the one or more nanosheet field-effect transistors and the gate of the one or more fin field-effect transistors.

Gate-all-around nanosheet field effect transistor integrated with fin field effect transistor

Embodiments of the invention include a dielectric reflow technique for boundary control in which a first layer is deposited on a first transistor region and a second transistor region, the first and second transistor regions being adjacent. A dielectric layer is formed to protect the second transistor region such that the first transistor region is exposed, the dielectric layer bounded at a first location. In response to removing a portion of the first layer on the first transistor region, the dielectric layer protecting the second transistor region is reflowed such that at least a reflowed portion of the dielectric layer extends beyond the first location.

Dielectric reflow for boundary control

A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FIN FET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

Embodiments of the invention are directed to a semiconductor-based structure that includes a stack having spaced-apart non-sacrificial nanosheets. A source or drain (S/D) trench is adjacent to the stack, wherein the S/D trench includes a bottom surface and sidewalls. A S/D template layer includes a continuous layer of a first type of semiconductor material, wherein the S/D template layer is within a portion of the S/D trench, on the bottom surface of the S/D trench, and on the sidewalls of the S/D trench. A doped S/D region is on the S/D template layer and within the S/D trench. In some aspects of the invention, the doped S/D region includes a second type of semiconductor material configured to induce strain in the spaced-apart non-sacrificial nanosheets.

Source or drain template for reducing strain loss in spaced-apart nanosheet channels

A semiconductor structure includes a p-type field-effect transistor region and an n-type field-effect transistor region. The p-type field-effect transistor region includes a strained channel of a composite of silicon germanium and silicon. The n-type field-effect transistor region includes a silicon channel.

Semiconductor device with strained channel

A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Three-dimensional field effect device

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Strained-channel fin FETs

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Method to induce strain in finFET channels from an adjacent region

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Guilderland, NY, United States of America

Nicolas J Loubet