Lam Research Corporation

Applied Materials, Inc.

Other

Nicolas J Bright

David J Hemker

Yehiel Gotkis

Rodney C Kistler

Jeffrey S Marks

Aleksander Owczarz

Kartik Ramaswamy

Yue Guo

Yang Yang

Kenneth S Collins

David Walter Groechel

Jeffrey C Benzing

A N M Wasekul Azad

Kenneth P MacWilliams

Jay E Uglow

Dave Hemker

Timothy M Archer

Michael Robert Rice

Tetsuya Ishikawa

Craig A Roderick

John R Trow

Andrew Nguyen

Yezdi N Dordi

Fritz C Redeker

S M Reza Sadjadi

Neil M Benjamin

Richard Alan Gottscho

Robert Steger

Chung-Ho Huang

Jian Ding

Benjamin W Mooring

Joshua Chiu-Wing Tsui

Bradley J Howard

Vladimir Katz

Srinivas D Nemani

Ellie Y Yieh

Andrew D Bailey, Iii

Thorsten B Lill

Alan M Schoepp

Peter R Keswick

Katsumasa Kawasaki

Tony Ray Kroeker

Fernando Silveira

Yifeng Zhou

Shih-Jeun Fan

Jackie Seto

Chan Lon Yang

Dave J Hemker

Joshua C-w Tsui

Kostiantyn Achkasov

Jamie Saephan

Chin Chuan Chang

Some embodiments are directed to a tuning circuit. The tuning circuit generally includes: a first impedance coupled between a first terminal and a second terminal of the tuning circuit, wherein the first terminal is coupled to a generator and the second terminal is coupled to a load; a second impedance coupled between the first impedance of the tuning circuit and a reference potential node; and a signal path coupled to the first impedance or the second impedance, the signal path comprising an inductive element and a first switch coupled to the inductive element, wherein a control input of the first switch is coupled to a control input of the tuning circuit configured to receive a control signal associated with a pulsed voltage (PV) waveform.

Radio-frequency (RF) matching network for fast impedance tuning

A semiconductor processing system may include a semiconductor processing chamber configured to execute a recipe on a semiconductor wafer. The system may include a first plasma source to provide plasma to the semiconductor processing chamber and to be duty cycled during an execution of the recipe. The system may also include a second plasma source configured to maintain the plasma in the semiconductor processing chamber while the first plasma source is duty cycled.

Auxiliary plasma source for robust ignition and restrikes in a plasma chamber

Embodiments of the disclosure provided herein include an apparatus and method for processing a substrate in a plasma processing system. The apparatus includes a pulse voltage (PV) waveform generator comprising at least one synchronization signal and a plurality of pulsers to provide a plurality of TTL inputs. The PV waveform generator generates a waveform containing pulses or bursts which contain micropulses corresponding to the plurality of TTL input signals and the at least one synchronization signal. The method includes receiving a first TTL input signal and a synchronization waveform signal from a controller, delivering a first micropulse to an electrode assembly after receiving the first TTL input signal and synchronization signal, and delivering a second micropulse to the electrode assembly after receiving the second TTL input signal and the synchronization signal.

System and methods for implementing a micro pulsing scheme using dual independent pulsers

A method and apparatus for spatially switching radio frequency (RF) power from a single RF power generator to a selected one of two or more impedance matching networks coupled to associated RF electrodes for forming plasma in a plasma chamber. Full RF power may be switched within microseconds to the selected one of the two or more impedance matching networks. The two or more impedance matching networks may be coupled to one or more plasma generating electrodes. The two or more impedance matching networks may be interleaved during plasma processing recipe operation. Impedance matching networks can alternate back and forth during operation of a plasma processing recipe. This interleaving in operation and impedance transformation capabilities may also be performed with more than two impedance matching networks, and may be beneficial in enabling the use of fixed tuned impedance matching networks instead of requiring variable impedance matching networks having variable tuning capabilities.

Radio frequency diverter assembly enabling on-demand different spatial

Embodiments of the disclosure include a method of processing a substrate in a plasma processing system, comprising delivering an RF signal, by an RF generator, through an RF match to an electrode assembly disposed within the plasma processing system, wherein while delivering the RF signal the RF match is set to a first matching point, and delivering a voltage waveform, by a waveform generator, to the electrode assembly disposed within the plasma processing system while the RF signal is delivered to the electrode assembly. The method includes receiving, by the RF match, a synchronization signal from a RF generator or the waveform generator, measuring, by an output sensor of the RF match, a first set of impedance related data of the plasma processing system over a first time period, the first time period beginning after a first delay triggered by a first portion of a first waveform pulse of the synchronization signal, measuring, by the output sensor of the RF match, a second set of impedance related data of the plasma processing system over a second time period, the second time period beginning after a second delay triggered by the first portion of the first waveform pulse of the synchronization signal, calculating, by the RF match, a combined impedance parameter based on the measured first set of impedance related data and the measured second set of impedance related data, and adjusting a matching parameter within the RF match based on the calculated combined impedance parameter to achieve a second matching point.

Scanning impedance measurement in a radio frequency plasma processing chamber

An apparatus for processing a substrate is disclosed and includes, in one embodiment, a twin chamber housing having two openings formed therethrough, a first pump interface member coaxially aligned with one of the two openings formed in the twin chamber housing, and a second pump interface member coaxially aligned with another of the two openings formed in the twin chamber housing, wherein each of the pump interface members include three channels that are concentric with a centerline of the two openings.

Chamber body design architecture for next generation advanced plasma technology

Methods and apparatus for processing a substrate are provided herein. For example, a matching network configured for use with a plasma processing chamber comprises an input configured to receive one or more radio frequency (RF) signals, an output configured to deliver the one or more RF signals to a processing chamber, a first sensor operably connected to the input and a second sensor operably connected to the output and configured to measure impedance during operation, at least one variable capacitor connected to the first sensor and the second sensor and a controller, based on a measured impedance, configured to tune the at least one variable capacitor of the matching network to a first target position based on weighted output impedance values measured at pulse states of a voltage waveform and to tune the at least one variable capacitor to a second target position based on weighted input impedance values measured at the pulse states of the voltage waveform.

Methods and apparatus for processing a substrate

Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.

Process integration scheme to lower overall dielectric constant in BEoL interconnect structures

Post etch treatments (PETs) of low-k dielectric films are described. For example, a method of patterning a low-k dielectric film includes etching a low-k dielectric layer disposed above a substrate with a first plasma process. The etching involves forming a fluorocarbon polymer on the low-k dielectric layer. The low-k dielectric layer is surface-conditioned with a second plasma process. The surface-conditioning removes the fluorocarbon polymer and forms an Si&#x2014;O-containing protecting layer on the low-k dielectric layer. The Si&#x2014;O-containing protecting layer is removed with a third plasma process.

Post etch treatment (PET) of a low-K dielectric film

In a plasma processing system, a method for dynamically establishing a baseline is provided. The method includes processing a first substrate. The method also includes collecting a first signal data for the first substrate. The method further includes comparing the first signal data against the baseline. The method moreover includes including the first signal data in a recalculation of the baseline if the first signal data is within a confidence level range, which is in between a top level above the baseline and a bottom level below the baseline.

Automatic dynamic baseline creation and adjustment

A method for affecting a creation of a recipe for processing a substrate in a processing system. The method includes providing a best-known method driven recipe editor. The best-known method driven recipe editor incorporates best-known methods (BKMs), which are best practice specifications for the recipe. The method also includes creating a plurality of BKM modules based on the BKMs for the recipe. The method further includes defining rules for parameters in the plurality of BKM modules. The rules are propagated by the BKMs. The methods moreover includes creating a BKM driven recipe by employing the best-known method driven recipe editor to enter values for the parameters within the guidelines of BKM rules.

Methods and arrangement for creating recipes using best-known methods

An apparatus comprising computer readable media is provided. The computer readable media comprises computer readable code for receiving a feature layout and computer readable code for applying shrink correction on the feature layout. The computer readable code for applying the shrink correction comprises providing corner cutouts, adjusting line width and length, shape modifications, etc. for forming features in a patterned layer.

Computer readable mask shrink control processor

A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry. The etching is timed to etch through a partial thickness of the low dielectric constant layer and the first etch chemistry is optimized to a selected low dielectric constant material. The method further includes forming a via hole in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In a specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

Methods for making dual-damascene dielectric structures

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Saratoga, CA, United States of America

Nicolas J Bright