Stmicroelectronics S.a.

Stmicroelectronics S.r.l.

Freescale Semiconductor,inc.

Stmicroelectronics Gmbh

Nicolas Grossier

Bruno Bernard

Ahmed Dabbagh

Stefano Pietri

Chris C Dao

Juxiang Ren

Thomas Alofs

V Srinivasan

Pierre-Yves Taloud

A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

System and method for controlling bypass of a voltage regulator

A computer system having a plurality of parallel execution pipelines which may generate data for storing in a memory, data from the pipelines may be stored in a queue prior to accessing the memory and the system includes circuitry for reordering data from the different pipelines before inserting onto the queue.

Method and apparatus for parallel execution pipeline data storage in a computer memory

A computer memory access controller receives load and store requests from a plurality of parallel execution pipelines and forms queues of store and load addresses. A comparator compares load addresses with store addresses in a store address queue and selects a store before load if an address match is found, but selects a load before a store if no address match is found.

Memory access in a computer system having parallel execution pipelines

A computer system with parallel execution pipelines and a memory access controller has store address queues holding addresses for store operations, store data queues holding a plurality of data for storing in the memory and load address storage holding addresses for load operations, said access controller including comparator circuitry to compare load addresses received by the controller with addresses in the store address queue and locate any addresses which are the same, each of said addresses including a first set of bits representing a word address together with a second set of byte enable bits and said comparator having circuitry to compare the byte enable bits of two addresses as well as said first set of bits.

Memory access address comparison of load and store queques

A memory for a computer system that includes a plurality of memory banks which provide an interleaved memory region as well as X and Y memory regions. Each memory access address includes a most significant set of bits indicating which of the interleaved, X, or Y memory regions is to be accessed. Each memory access address also includes a least significant set of bits indicating an address within the bank of the access region. At least one bit in the least significant set is a bank selector and one bit of the most significant set of bits is an X or Y region selector.

Computer memory access

A circuit for controlling the storage of data in a memory element including a bistable device having a first input for receiving an address input and a second input for receiving a clock signal and circuitry for receiving the output of the bistable device and the clock signal and providing a write enable signal for the memory, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, the first and next transitions being in the same clock cycle.

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St Georges de Commiers, France

Nicolas Grossier