Applied Materials, Inc.

Lam Research Corporation

Other

Nicolas Gani

Meihua Shen

Radhika C Mani

Noel Sun

John Patrick Holland

Shashank C Deshmukh

Alex Paterson

Theodoros Panagopoulos

Yoshie Kimura

Gowri Kamarthy

Monica Titus

Helene Del Puppo

Do Young Kim

Oranna Yauw

Jen-Kan Yu

Ting-Ying Chung

Ellie Y Yieh

Wei Liu

Thorsten B Lill

Jeffrey D Chinn

Valentin Nikolov Todorow

Anisul Haque Khan

Weimin Zeng

Dan Katz

Sunil Srinivasan

Alexander Matyushkin

Uday Mitra

Denis M Koosau

Hiroki Sasano

Chung Liu

Hakeem M Oluseyi

Daehee Weon

Yan Du

Michael Hegarty

Thomas Joseph Kropewnicki

Wilfred Pau

Han-Hsiang Chen

Eric Pei

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Internal plasma grid applications for semiconductor fabrication

Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.

Methods for in-situ chamber clean utilized in an etching processing chamber

Methods of polysilicon over-etch using hydrogen diluted plasma for three-dimensional gate etch are described. In an example, a method of forming a three-dimensional gate structure includes performing a main plasma etch on a masked polysilicon layer formed over a semiconductor fin. The method also includes, subsequently, performing a plasma over etch on the masked polysilicon layer based on a plasma generated from gaseous composition including hydrogen gas (H).

Polysilicon over-etch using hydrogen diluted plasma for three-dimensional gate etch

Internal plasma grid applications for semiconductor fabrication in context of ion-ion plasma processing

Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl, setting the temperature of the wafer to be between 100&#xb0; C. and 350&#xb0; C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl, setting the temperature of the wafer to be between 20&#xb0; C. and 200&#xb0; C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl, setting the temperature of the wafer to be between 20&#xb0; C. and 200&#xb0; C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.

Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries

Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.

Shallow trench isolation etch process

Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.

Method for fabricating a semiconductor device having a lanthanum-family-based oxide layer

Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.

Alternative method for advanced CMOS logic gate etch applications

Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate, and etching the substrate on the preferentially regulated substrate support. In another embodiment, the method includes providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set, etching a first layer of material and etching a second layer of material respectively using different control parameter sets.

Method for etching having a controlled distribution of process results

A pedestal assembly and method for controlling temperature of a substrate during processing is provided. In one embodiment, the pedestal assembly includes an electrostatic chuck coupled to a metallic base. The electrostatic chuck includes at least one chucking electrode and metallic base includes at least two fluidly isolated conduit loops disposed therein. In another embodiment, the pedestal assembly includes a support member that is coupled to a base by a material layer. The material layer has at least two regions having different coefficients of thermal conductivity. In another embodiment, the support member is an electrostatic chuck. In further embodiments, a pedestal assembly has channels formed between the base and support member for providing cooling gas in proximity to the material layer to further control heat transfer between the support member and the base, thereby controlling the temperature profile of a substrate disposed on the support member.

Method and apparatus for controlling temperature of a substrate

Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

High selectivity and residue free process for metal on thin dielectric gate etch application

A method and apparatus for operating a matching network within a plasma enhanced semiconductor wafer processing system that uses pulsed power to facilitate plasma processing.

Method and apparatus for tuning an RF matching network in a plasma enhanced semiconductor wafer processing system

A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power. The first source gas and first substrate bias power provide a higher etch rate in dense feature areas than in isolated feature areas during the main etch step, whereas the second source gas and second substrate bias power provide a higher etch rate in isolated feature areas than in dense feature areas during the overetch step, resulting in an overall balancing effect.

Method of etching organic antireflection coating (ARC) layers

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San Jose, CA, United States of America

Nicolas Gani