Mitsubishi Electric Corporation

Mitsubishi Electric R&d Centre Europe B.v.

Nicolas Degrenne

Stefan Mollov

Jeffrey Ewanchuk

Julio Brandelero

Nicolas Gresset

Nicolas Voyer

Laurent Foube

Guilherme Bueno Mariani

Vincent Quemener

Pierre-Yves Pichon

Merouane Ouhab

Julio Cezar Brandelero

The present disclosure relates to a method for estimating parameters of a junction of a power semi-conductor element comprising: •—Detecting at least one stable on-line operating condition through measurements () of Von, Ion, Tc on a semi-conductor module () where Ion is a current for which the on-state voltage Von of the semi-conductor is sensitive to the temperature and Tc is the temperature of the casing of said semi-conductor element; •—Measuring and storing at least one parameter set Von, Ion, Tc of said at least one stable operating condition; •—in a calculating unit (), providing calculations for minimizing the error between a junction temperature estimation Tj of an electrical model Tj=F(Von, Ion, θelec) comprising a first set of unknown parameters θelec and another junction temperature estimation Tjmod of a loss/thermal model Tj=G(Ion, Tc, θ mod) comprising a second set of unknown parameters θ mod and obtaining at least one set of parameters θelec and at least one parameter θ mod providing minimization of said error; •—providing the calculated value of Tj with at least one of the calculated parameters sets θelec and/or θ mod and the measured Von, Ion, Tc; •—Storing the at least one parameters set θelec and/or θ mod and/or Tj.

Method for estimating parameters of a junction of a power semi-conductor element and power unit

The present invention concerns a method and device for monitoring the gate signal of a power semiconductor (SI), the gate signal of the power semiconductor (SI) being provided by a gate driver (), generates an expected signal (VGexp) that corresponds to the signal outputted by the gate driver () when no deterioration of the gate driver () and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists, compares the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (), determines if a deterioration of the gate driver () and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists using the result of the comparing of the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver ().

Method and device for monitoring gate signal of power semiconductor

Power semi-conductor module () comprising: —at least one IGBT with a Gate G forming a first electrode () and an Emitter E forming a second electrode (), or —at least one MOSFET with a Gate G forming a first electrode () and a Source S forming a second electrode (). The first electrode () includes a polysilicon material made in one piece. The one-piece is made partly of a monitoring portion (). The monitoring portion () is in electrical contact with the second electrode () such that a leakage current flows between the first electrode () and the second electrode () in an operational state of the module (). The monitoring portion () has a location, a form, a size and a material composition selected together such that to have a variable resistance in function of its temperature during the operational state of the module ().

Power semi-conductor module, mask, measurement method, computer software, and recording medium

A method for estimating degradation of a wire-bonded power semi-conductor module is provided. The method includes obtaining an indicator of degradation (Degr); estimating an estimated indicator of degradation (Degr) by a temporal degradation model; obtaining a set of on-line measure (X); then, (1) converting the on-line measure (X) into a deducted indicator of degradation (Degr) by an electrical equivalence model, and (2) computing a deviation between estimated and deducted indicator of degradation (Degr; Degr); and/or (1) converting the estimated indicator of degradation (Degr) into a set of on-line estimation (X), and (2) computing a deviation between set of on-line measure and estimation (X; X); and correcting the estimated indicator of degradation (Degr) into a corrected estimated indicator of degradation (Degr) as a function of the computed deviation.

Method for estimating degradation of a wire-bonded power semi-conductor module

A device having at least one power semiconductor die coated with a metallization and at least one light guide having two opposite ends. The first end is able to be connected at least to a light source and to a light receiver. The second end is permanently fixed facing to a surface of the metallization such that to form a light path towards said surface and a light path from said surface.

Device and method for monitoring the health of a power semiconductor die

An inductive assembly includes: a support with an open channel having a straight portion with a bottom surface and two side surfaces, a foldable PCB such that to cover at least a part of the bottom surface and the side surfaces, the PCB having a plurality of tracks, each track being electrically continuous between a pair of connecting spots, a magnetic piece which can be accommodated into the channel equipped with the PCB. The PCB is arranged to surround at least partially a portion of the magnetic piece in the folded state in the channel such that at least one connecting spot of a first track is electrically connected to a connecting spot of a second track to form a winding around the magnetic piece and to inductively couple the PCB and the magnetic piece.

Inductive assembly and method of manufacturing inductive assembly

A method to establish a degradation state of electrical connections in a power semiconductor device comprising:

Diagnostic device and method to establish degradation state of electrical connection in power semiconductor device

The present invention concerns a device for controlling the switching of a first and a second power semiconductor switches providing current to a load in a half bridge configuration. The device comprises: means for obtaining a first current value through the first switch or the load just before the switching of the first switch from conducting to non-conducting state, means for limiting the current through the second switch during the switching of the second switch from non-conducting to conducting state using the obtained first current value, by modifying the gate signal of the second switch, means for obtaining a second current value through the second switch or the load just before the switching of the second switch from conducting to non-conducting state, means for limiting the current through the first switch during the switching of the first switch from non-conducting to conducting state using the obtained second current value by modifying the gate signal of the first switch.

Device and method for controlling switching

The present invention relates to a printed circuit board embedding a power die wherein interconnections between the power die and the printed circuit board are composed of micro/nano wires, the printed circuit board comprising a cavity wherein the power die is placed, and wherein the cavity is further filled with a dielectric fluid.

Printed circuit board and method for manufacturing printed circuit board

A method estimates a level of damage or a lifetime expectation of a power semiconductor module having at least one die that is mechanically and electrically attached to a ceramic substrate. The ceramic substrate has piezoelectric properties and the method includes: controlling the at least one power die, the control of the at least one power die generating changes in the electrical potential across the ceramic substrate; obtaining information representative of a mechanical deformation of the ceramic substrate; determining if a notification indicating the level of damage or the lifetime expectation has to be performed according to the obtained information and reference information; and notifying the level of damage or the lifetime expectation if the determining step determines that the notification has to be performed.

Method and device for estimating level of damage or lifetime expectation of power semiconductor module

The present invention concerns a method for estimating a level of damage of an electric device. The method comprises the steps of: forming a histogram of operating cycles related to the electric device for which the level of damage estimation is performed, comparing the formed histogram to histograms of a collection of histograms or to combinations of histograms of the collection of histograms, each histogram of the collection of histogram being associated to a level of damage, in order to determine the histogram of the collection of histograms or the combination of histograms which is the closest from the formed histogram, determining an estimate of the level of damage of the electric device from the level of damage of the closest histogram or from the levels of damages of the histograms of the closest combination of histograms.

Method, device and system for estimating level of damage of electric device using histograms

The present invention concerns a method and a device for estimating a level of damage or a lifetime expectation of a power semiconductor module comprising at least one die that is mechanically, thermally, and electrically attached to a substrate, composed of plural layers of different materials. The invention:

The present invention concerns a power module comprising a heat sink, a substrate on which a power die is attached, the power module further comprises between the substrate and the heat sink, a first and a second materials, the first material having a thermal conductivity that is higher than the thermal conductivity of the second material, the second material having a first cavity below the power die and the first material is in the first cavity of the second material.

Power module and method for manufacturing power module

The present invention concerns a system for determining if a deterioration occurs in an interface of a semiconductor die of an electric power module, the electric power module further comprising a substrate and at least one electromechanical transductor, the semiconductor die and the at least one electromechanical transductor being placed on or embedded within the substrate, wherein the system comprises: &#x2014;means for transferring at least one electric signal to the at least one electromechanical transductor, &#x2014;means for measuring the impedance of the at least one electromechanical transductor, &#x2014;means for comparing the impedance of the at least one electromechanical transductor to a predetermined value, &#x2014;means for deciding that the deterioration occurs in the interface of the semiconductor die according to the comparison result.

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Rennes, France

Nicolas Degrenne