International Business Machines Corporation

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Nicolas Degors

Terence B Hook

Kangguo Cheng

Ahmet Serkan Ozcan

Shawn Peter Fetterolf

Francois Andrieu

Pierre Perreau

A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

Channel silicon germanium formation method

The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Semiconductor device with low band-to-band tunneling

There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS transistor formed on the insulating layer and including a channel formed in a first layer of a silicon&#x2014;germanium alloy, having a first thickness and first average germanium density; a gate oxide layer having a first equivalent oxide thickness; a second pMOS transistor formed on the insulating layer and further including a channel formed in a second layer of a silicon&#x2014;germanium alloy, having a second thickness which is greater than the first and a second average germanium density which is lower than the first; and a gate oxide layer having a second equivalent oxide thickness which is greater than the first.

Integrated circuit comprising PMOS transistors with different voltage thresholds

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Le Versoud, France

Nicolas Degors