Beelinx Usa, LLC

Silicon Laboratories Inc.

Koninklijke Philips Corporation N.v.

Nicolas Constantinidis

Guillaume Crinon

Didier Gallais

Alan Lee Westwick

Alexandre Rouxel

Gary Franzosa

Marty Lynn Pflum

Konstantinos Manetakis

Sylvain Chabanne

An embodiment of a mobile communication system includes a plurality of mobile units operating within a defined operating area, each of the mobile units having a processor, a memory for storing a mobile unit file structure, an application running on the processor for operating on the mobile unit file structure, and a receiver for receiving on a common receive communication channel data. The mobile communication system further includes a plurality of geolocation markers disposed within the defined operating area, each having a memory for storing geolocation information to define a relative position within the defined operating area, and a geolocation transmitter for transmitting the defined geolocation information on the common receive communication channel, the geolocation transmitter having a geolocation transmit range less than the defined operating area.

Urban mobile network system

A mobile network comprising a central unit () for communicating with a first network (); at least one intermediate base station () for communication with the central unit () over the first network () and for transmitting data to a second network; at least one mobile unit () for receiving data from the base station over the second network, a memory for storing the data, a display and a processor running an application to display at least a portion of the stored data; and at least one geolocation marker () external to the mobile unit for generating a signal including position information indication a relative position, wherein the signal is received by the mobile unit when it is proximate to the base station wherein the central unit broadcasts at least one portion of the data to the mobile unit through the intermediate base station; and wherein the application running on the processor displays a portion of the stored data associated with the relative position.

A single chip radio platform is disclosed for communicating with an RF channel. An RF front end is provided having a receive/transmit capability to receive an RF carrier modulated with digital data and convert the data to analog baseband data, and modulate an RF carrier with baseband data. A digital signal processor (DSP) engine is provided for interfacing with the RF front end to form in conjunction therewith the PHY layer, and interfacing with the MAC layer to demodulate the baseband data and in the transmit mode to generate the baseband data for modulation and transmission by the RF front end. A microcontroller unit (MCU) is provided for performing the functionality of the MAC, network and application layers and interfacing with the DSP. Clock circuitry is provided including a stable reference clock for generating a first fixed clock for providing MCU clocks for the operation of the MCU, and for providing a reference for a local oscillator at substantially the channel frequency for use by the RF front end and a DSP clock for use by the DSP, both the MCU clocks, the local oscillator and the DSP clock having the stability of the first fixed clock. Periodic power management circuitry is provided for controlling the operation of the radio platform to operate in a sleep.

Single chip low power fully integrated 802.15.4 radio platform

A method is disclosed for controlling the operation of a low power radio platform that realizes the physical layer (PHY) with a software portion and an analog front end, the analog front end disposed between the DSP and an antenna, and realizes the MAC layer with a microcontroller unit (MCU). The DSP, analog front end and MCU are maintained in a low power mode of operation when not in data communication. When data communication is initiated, a hardware controller controls at least one hardware interface disposed between the DSP and the analog front end to initiate multiple time based tasks to transfer data to and from a buffer. During the execution of these tasks, the controller causes a task in the DSP to be initiated for processing of data in the buffers and, upon completion of at least one of the tasks, notifying the MCU of such. The controller controls the hardware interface to terminate operation when predetermined time based events have occurred. The MCU in at least one mode of operation thereof is operable to initiate the operation of the hardware controller and then convert to a low power mode of operation to await notification.

Hardware synchronizer for 802.15.4 radio to minimize processing power consumption

A charge pumped phase locked loop circuit (PLL) is disclosed that includes a phase detector for detecting the phase error between a reference clock and an output clock to generate a phase error signal. A charge pump is provided that is controlled by the phase error signal to either source current to an intermediate control node or to sink current therefrom. An isolation circuit maintains the intermediate control node at a virtual AC reference voltage such that it remains at substantially the same voltage during the sourcing of current thereto or sinking of current therefrom, the isolation circuit generating a control voltage on the output thereof to control the frequency of the output clock. A loop filter is provided for filtering the control voltage.

Integrated PLL loop filter and charge pump

An apparatus and method for comparing the amplitudes of two electric signals Iout and Qout are disclosed. The method includes a step wherein powers conveyed by the signals Iout and Qout are compared. One feature of the method and apparatus is that it is not necessary to storing the maxima of the signals to be compared when these signals are out of phase with respect to each other. One application of the method or apparatus is for the correction of differences in amplitude between I, Q signals that are separated in phase by 90&deg; inside QAM, QPSK or QBSK demodulators.

Method of comparing the amplitudes of two electric signals

The invention relates to an amplification device AD, comprising a first and a second amplifier AMP and AMP arranged in cascade, each amplifier being provided with a feedback loop Zi (where i&equals;1 or 2) and having a gain proper Gi equal to Ai/(1&plus;Ai.Zi). In accordance with the invention, the value of the inverse of the gain proper Gi of the first amplifier AMP is substantially equal to three times the value of the inverse of the gain proper G of the second amplifier AMP raised to the power of three: (1/G )&equals;3/(G ) . Such a choice provides the amplification device AD with an optimum linearity.

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Cresserons, France

Nicolas Constantinidis