Safran Electronics & Defense

Sagem Defense Securite

Nicolas Charrier

Nicolas Marti

Michael Montoya

Celine Liu

Eric Karniewicz

Céline Liu

Christophe Poilvet

An on-board computer includes a microprocessor chip with a lower face and an upper face, a chip carrier having an upper face on which the microprocessor chip is mounted, and a casing configured to discharge heat generated by the microprocessor chip in operation. An interposer is disposed between the upper face and the casing. The interposer diffuses the heat transmitted by the upper face of the microprocessor chip towards the casing. The interposer has an upper surface for heat exchange with the casing that is twice or more greater than the surface area of the upper face of the microprocessor chip. The interposer has on one or more sides a peripheral wedging rim coming into contact with a side wall of the chip carrier, and has no more than two peripheral wedging rims, in order to leave the other sides of the interposer free.

On-board computer with interposer on the microprocessor chip

The invention relates to: Control circuit () for an electrical device (), said control circuit () receiving as input a discrete electrical control signal (CMD), the control circuit () comprising a source () of voltage (&#xb1;V) configured so as to supply the circuit according to a negative or positive voltage; a switch () normally closed in the absence of any discrete electrical control signal (CMD) and configured so as to isolate the electrical device from the voltage source as a function of the electrical control signal (CMD), said switch being connected between the voltage source and the electrical device (); the switch () being sensitive to the discrete electrical control signal (CMD) for just one sense of voltage.

Electrical circuit for control of an electrical device with high integrity

The invention concerns a bandwidth control method in an on-chip system comprising at least one main master module, at least one secondary master module, at least one slave module and a bus connected to each module on a communication link, the bus comprising interconnection means to make at least one common slave module communicate with at least one main master module and with at least one secondary master module via at least one common path portion, the method comprising the following steps carried out for each common slave module: first detection of a first request to access the common slave module, issued by a main master module, definition of a blocking time Dj associated with the common slave module, blocking, during blocking time Dj, of any data transfer on the at least one common path portion between a secondary master module and the common slave module.

Bandwidth control method for an on-chip system

Growing community of inventors

Boulogne-Billancourt, France

Nicolas Charrier