Stmicroelectronics S.r.l.

Stmicroelectronics Application Gmbh

Stmicroelectronics International N.v.

Freescale Semiconductor,inc.

Nicolas Bernard Grossier

Roberto Colombo

Fabio Enrico Carlo Disegni

Giovanni Disirio

Deepak Baranwal

Vivek Mohan Sharma

Lorenzo Re Fiorentin

Roberta Vittimani

Samiksha Agarwal

Carl Culshaw

Pasqualina Fragneto

Thomas Henry Luedeke

Avneep Kumar Goyal

Lorenzo Guerrieri

Asif Rashid Zargar

Giovanni Di Sirio

V Srinivasan

Charul Jain

Thomas Szurmant

Sabyasachi Das

Giuseppe Livio Gobbato

Daniele Zerbini

Martina Cordoni

In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

Processing system, related integrated circuit, device and method

A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down. During the software runtime phase, the first circuitry activate a weak pull-down for implementing a bidirectional reset terminal or activates a weak pull-up resistance for implementing a reset output terminal, and the second circuitry activates a weak pull-up for implementing a reset input terminal or activates a strong pull-up for implementing a reset output terminal.

A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

Hardware secure element, related processing system, integrated circuit, and device

In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.

Circuit and method for capturing and transporting data errors

A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

High speed debug-delay compensation in external tool

A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.

Hardware secure element, related processing system, integrated circuit, device and method

In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first memory error packet associated with a first memory; receiving, with the first buffer, a second memory error packet associated with a second memory; transmitting a first reading request for reading the first memory error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central memory error management unit (MEMU); in response to receiving the first reading request, reading the first memory error packet from the first buffer, transmitting the first memory error packet to a controller of the central MEMU, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second memory error packet.

In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.

A semiconductor device, for example an integrated circuit such as a microcontroller (MCU) or a digital signal processor (DSP), includes a semiconductor die coupled with a power supply line, a debug module coupled with the semiconductor die to exchange semiconductor die debug command and data signals with the semiconductor die, and a modem coupled with the power supply line. The debug module is arranged to convey the semiconductor die debug command and data signals over the power supply line.

Semiconductor device and corresponding debugging method

A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.

Microprocessor device, and method of managing reset events therefor

A Voltage regulator includes a first input terminal configured to receive an input supply voltage, includes a second input terminal configured to receive a regulated output supply voltage as a function of the input supply voltage or to receive a test supply voltage and comprises a power transistor including an input terminal configured to receive the input supply voltage and including an output terminal configured to generate the regulated output supply voltage. The Voltage regulator is configured, during a start-up phase of a test operation mode, to receive a control signal equal to the input supply voltage, is configured to receive the input supply voltage having a substantially increasing trend, detect that the input supply voltage is equal to a first voltage threshold and generate, as a function of the detected signal and of the control signal, a by-pass signal having a transition from a first logic value to a second logic value for indicating a by-pass status of the Voltage regulator, and is configured to receive the by-pass signal having the second logic value and open the power transistor. The second input terminal is configured, during the test operation mode, to receive the test supply voltage having a test value different from a nominal value of the regulated output supply voltage.

Growing community of inventors

Oreno di Vimercate, Italy

Nicolas Bernard Grossier