International Business Machines Corporation

Nicolas Antoine

Ahmet Serkan Ozcan

Carl John Radens

Charles Edwin Cox

Pritish Narayanan

Tomasz Kornuta

Alexis Asseman

A system according to one embodiment includes a collection of computing nodes arranged in a mesh of N&#xd7;M&#xd7;Z topology, the nodes including computational hardware, wherein Z&#x3c;N and Z&#x3c;M, and wherein N and M are at least equal to 4; a collection of I/O connections interfaced with one of the sides of the mesh, said side having N&#xd7;M nodes, each of the I/O connections being tied to a unique one of the nodes in said side; and I/O cards that are tied to the I/O connections.

Configuring computing nodes in a three-dimensional mesh topology

A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

Distributed memory-augmented neural network architecture

A computer-implemented method is provided for use with a reconfigurable computational device having a collection of computing nodes arranged in a mesh of N&#xd7;M&#xd7;Z topology, the computing nodes including computational hardware, wherein Z&#x3c;N and Z&#x3c;M, and wherein N and M are at least equal to 4. The method includes using the computational device to perform computations characterized by (i) an initial system I/O bandwidth and (ii) an initial system node-to-node latency; reconfiguring the device into a mesh of N'&#xd7;M&#x2032;&#xd7;Z&#x2032; topology, wherein at least two of N, M, and Z values are different from their corresponding N&#x2032;, M&#x2032;, and Z&#x2032; values, and wherein N&#xd7;M&#xd7;Z is equal to N&#x2032;&#xd7;M&#x2032;&#xd7;Z&#x2032;; and using the device to perform computations characterized by (i) a modified system I/O bandwidth and (ii) a modified system node-to-node latency.

Growing community of inventors

San Jose, CA, United States of America

Nicolas Antoine