Stmicroelectronics S.r.l.

Stmicroelectronics S.a.

Nicola Zatelli

Federico Pio

Alfonso Maurelli

Carlo Cremonesi

Paolo Giuseppe Cappelletti

Elisabetta Palumbo

Mathieu Pierre Lisart

Bruno Vajana

Laurent Sourgen

Cesare Clementi

Cosimo Torelli

Daniela Peschiaroli

Barbara Crivelli

Massimo Ati

Massimo Atti

The method applies to non-volatile semiconductor memories with cells arranged in rows and in columns, in which each cell has a first terminal, a second terminal, and a third terminal connected, respectively, to a row line, to a column line, and to a common node by respective connection strips. In order to form connections with low resistivity and consequently to save semiconductor area, the method provides for the formation of an oxide layer which covers the connection strips of the first terminals and of the third terminals, the formation of channels along the connection strips until the surfaces thereof are exposed, and the filling of the channels with a material having a resistivity lower than that of the connection strips.

Method of forming low-resistivity connections in non-volatile memories

A lateral DMOS transistor having a drain region which comprises a high-concentration portion with which the drain electrode is in contact and a low-concentration portion which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode in contact with a point of the low-concentration portion of the drain region which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

Lateral DMOS transistor with first and second drain electrodes in respective contact with high-and low-concentration portions of a drain region

The memory cell is of the type with a single level of polysilicon, and comprises a sensing transistor and a select transistor. The sensing transistor comprises a control gate region with a second type of conductivity, formed in a first active region of a substrate of semiconductor material, and a floating gate region which extends transversely relative to the first active region. The control gate region of the sensing transistor is surrounded by a first well with the first type of conductivity, and in turn is surrounded, below and laterally, by a second well with the second type of conductivity, thus forming a triple-well structure. A second triple-well structure can be formed in a second active region adjacent to the first active region, and can accommodate conduction regions of the sensing transistor and of the select transistor.

EEPROM type non-volatile memory cell and corresponding production method

The memory cell is of the type with a single level of polysilicon, and is produced in a substrate of semiconductor material with a first type of conductivity, and comprises a control gate region with a second type of conductivity, formed in the substrate in a first active region; regions of source and drain with the second type of conductivity, formed in the substrate in a second active region; and a floating gate region which extends transversely relative to the first and the second active regions. The control gate region is surrounded by a first well with the first type of conductivity, which in turn is surrounded, below and laterally, by a third well with the second type of conductivity. The regions of source and drain are accommodated in a second well with the first type of conductivity, which in turn is surrounded below and laterally by a fourth well with the second type of conductivity.

Non-volatile memory cell with a single level of polysilicon, in particular of the flash EEPROM type, and method for manufacturing the same

A serial-flash, EPROM, EEPROM, or flash EEPROM nonvolatile memory in AMG configuration includes a byte enable transistor having an input terminal, connected to a control gate line and receives an input voltage, an output terminal, connected to at least one memory cell and supplying an output voltage, a control terminal connected to a word line, and a bulk region housing conductive regions connected to the input and output terminals. The byte enable transistor is a P-channel MOS transistor, the bulk region whereof is biased to a bulk voltage that is not lower than the input voltage.

Serial-flash, EPROM, EEPROM and flash EEPROM nonvolatile memory in AMG configuration

Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.

Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage

The structure allows checking an integrated electronic device comprising an oxide layer to be measured located above a doped pocket of a wafer of doped semiconductor material and arranged adjacent to a gate region of polycrystalline semiconductor material. The structure is formed at a suitable point of the wafer and comprises an oxide test region of the same material, having the same thickness and the same electrical characteristics as the oxide layer to be measured and a polycrystalline region of the same material, having the same thickness and the same electrical characteristics as the gate region. The polycrystalline region extends preferably along the perimeter of a square and delimits laterally the oxide test region, the area of which is greater than the area of the oxide layer to be measured so as to allow non-destructive testing, on-line, of the oxide layer to be measured during an early stage of the manufacturing process.

Structure and method for evaluating an integrated electronic device

A nonvolatile semiconductor memory device structure having a matrix of memory cells in a semiconductor material layer. The memory cells are located at intersections of rows and columns of the matrix. Each memory cell includes a control gate electrode connected to one of the rows, a first electrode connected to one of the columns and a second electrode. The rows comprise polysilicon strips extending parallel to each other in a first direction, and the columns are formed by metal strips extending parallel to each other in a second direction orthogonal to the first direction. Short-circuit metal strips are coupled for short-circuiting the second electrodes of the memory cells. The columns and the short-circuit strips arc respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated by a dielectric layer.

Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips

The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.

Process for manufacturing selection transistors for nonvolatile serial-flash, EPROM, EEPROM and flash-EEPROM memories in standard or AMG configuration

Process for manufacturing a non-volatile memory with memory cells arranged in rows and columns in a matrix structure, with source lines extending in parallel with and intercalated to said rows, the cells including MOS transistors having a floating gate and a control gate respectively formed in a first and a second polysilicon layers superimposed, the process including a first step of definition of regions of active area covered by a layer of thin oxide and delimited by regions of field oxide, a second step of deposition of the first polysilicon layer, a third step of etch of the first polysilicon layer through a first mask to separate the floating gates of cells belonging to a same row of the matrix, a fourth step of deposition of an intermediate dielectric layer and of the second polysilicon layer, a fifth step of definition of the rows through self-aligned selective etch of said second polysilicon layer, of the intermediate dielectric layer and of the first polysilicon layer, the self-aligned selective etch determining in the source lines excavations in correspondence of regions in which the first polysilicon layer has been removed during the third step, and a sixth step of dopant introduction in the regions of active area for the formation of regions of source and drain of the cells. Before the fourth step a selective introduction of dopant is provided in correspondence of regions of the common source lines in which the excavations will be formed, for the formation of doped regions deeper than the excavations.

Process for manufacturing of a non volatile memory with reduced resistance of the common source lines

An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

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Bergamo, Italy

Nicola Zatelli