Rca Inc.

General Electric Company

Thomson Multimedia S.a.

Technology Inc. 64

Intel Corporation

Xilinx, Inc.

Thomson Consumer Electronics Inc.

Sarnoff Corporation

Nicola J Fedele

Alfonse Anthony Acampora

David L Sprague

Lawrence D Ryan

Robert A Dischert

Paul Wallace Lyons

Kevin Harney

Allen H Simon

Victor Vincent D'Alessandro

Michael F Patti

Rajesh Hingorani

Brian Astle

Glenn A Reitmeier

John M Keith

Bhavesh B Bhatt

Richard Michael Bunting

Ted N Altman

Richard M Bunting

Harvey Waldman

Paul Hashfield

Peter J Burt

David Paul Bortfeld

Steven Kennedy Evans

A circuit for encoding a data stream is described. The circuit comprises a non-zero count circuit coupled to receive the data stream and output a count of non-zero coefficients of a block of data of the data stream; a trailing ones detection circuit coupled to receive the data stream and output a number of trailing ones of the block of data; and a memory coupled to the non-zero count circuit and the trailing ones detection circuit and storing encoded data values, the memory outputting an encoded data value for a non-zero coefficient of a block of data based upon the count of non-zero coefficients and the number of trailing ones for the block of data. A method of encoding a data stream is disclosed.

Circuit for and method of encoding a data stream

A method and apparatus for providing a composite of stored dynamic background activities with newly filmed or captured live foreground activities, thereby providing a real-time and on-site guide to actors and directors.

Apparatus and method for producing images using digitally stored dynamic background sets

Image signals are transcoded from a first format to a second format, by employing multi-tap horizontal and vertical filters. The first format has higher horizontal and vertical resolution than the second format. The multi-tap horizontal filter filters lines of the image signals to convert the horizontal resolution of the first format into the horizontal resolution of the second format, wherein the horizontal filter has a filter tap ratio selected in accordance with the horizontal ratio of the first format to the second format. The multi-tap vertical filter for filtering columns of the image signals to convert the vertical resolution of the first format into the vertical resolution of the second format, wherein the vertical filter has a filter tap ratio selected in accordance with the vertical ratio of the first format to the second format.

HDTV to NTSC transcoder system

A method is disclosed for optimizing the operation of a packet transport system generating a packet stream carrying a plurality of component signals, and includes the following steps. First the packet stream is partitioned into successive groups, each group containing a predetermined number of packet slots. A plurality of lists are maintained, one associated with each packet slot in a group. A packet stream is generated by placing data representing a component signal selected in response to entries in the list associated with that packet slot into the packet slot. The contents of the plurality of lists are updated based on a predetermined parameter.

Optimizing performance in a packet slot priority packet transport system

A transport stream encoder is disclosed which comprises a plurality of FIFO buffers coupled to sources of component signals. Each of the FIFO buffers has a data output terminal for producing component signal data. A packetizer has a data input terminal for receiving component signal data, and produces a packet stream. A data bus is coupled in common to the data output terminals of the FIFO buffers and the data input terminal of the packetizer.

Easily expandable transport stream encoder

A method and apparatus are disclosed for operating a transport stream encoder to produce a stream of packets carrying data representing a plurality of component signals which comprises the following steps. The packet stream is partitioned into successive groups, each group containing a predetermined number of packet slots. A plurality of priority lists is maintained, one for each of the packet slots in the group. Each priority list contains a plurality of entries, and each entry identifies one of the component signals. When a packet slot is to be produced, the entries in the priority list corresponding to that packet slot are traversed, one at a time. For each of those entries it is determined whether the component signal identified by that entry can produce a packet. If it can, a packet containing data representing that component signal is produced. Only if none of the component signals identified by the entries in the priority list can produce a packet is a null packet produced.

Method and apparatus for operating a transport stream encoder to produce

An adaptive scan format converter (14, FIG. 1; FIG. 2) at a transmitter/encoder of a video signal processing system such as a high definition television (HDTV) system, as a function of what format is desired for coding and transmission via an output channel. Similarly, at a receiver, a received scan format is automatically converted (36, FIG. 1; FIG. 2) to a desired format for display as needed. For example, a received interlaced signal (I) will be automatically converted to progressive (P) format to be compatible with a progressive scan display device (39). A received progressive signal will be passed to the display device without format conversion. Automatic scan conversion is performed seamlessly so that, for example, the conversion between progressive main television program material and interlaced commercial material is produced without artifacts and is essentially invisible to a viewer.

Image scanning format converter suitable for a high definition

A video signal processor includes cicuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuiry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.

Dual mode combining circuitry

A video signal processor includes circuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuitry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.

Dual mode adder circuitry with overflow detection and substitution

Variable-length codewords are grouped into successive N bit word groups in sequential order as received from a variable length codeword encoder. The N-bit groups are each stored in corresponding N-bit-wide memory locations in a buffer memory prior to transmission over a channel. The locations are filled to capacity on one clock pulse and emptied on a second clock pulse to efficiently utilize the memory at a given clock rate.

Apparatus for efficiently packing data in a buffer

A line marker signal is added to a DPCM encoded video signal to mark the beginning of each video scan line. The receiver searches for this marker signal and counts pixels between received markers, each scan line having a known number of pixels. The pixel count is checked against the known number of pixels in an error free system. If the pixel count differs from the known count, an error is indicated. The line marker signal is used to reset the decoder so the receiver is resynchronized at each scan line.

Error detector for encoded digital signals

A computer system has a central processing unit and a video display processor both of which must directly access the system memory. The display processor must access the memory once in a given time period which time period is long enough that several accesses by the central processing unit and the display processor would be possible. The system includes a memory controller which allows the central processing unit to have memory access priority over the display processor, as long as sufficient time remains in the period for the display processor to complete its access after the access by the processing unit. If insufficient time remains, the display processor has priority for memory access. To implement this priority scheme, a new system memory organization is employed, dividing the memory into banks or bit planes and providing each bank with a respective temporary storage latch that loads to a respective shift register. The serial data stream from the shift registers supply the video display processor video code information on a continuing basis. The timing of memory read out to the temporary storage latches is timed in accordance with the memory priority protocol.

Computer device display system using conditionally asynchronous memory

In a DPCM video digital data communication system, each scan line of a video frame is refreshed with PCM data over a refresh cycle comprising a plurality of frames. Refresh generators at the transmitter and at the receiver are synchronized with an initialization signal and with subsequent refresh cycle synchronizing signals. Also the scan lines and frames are synchronized with corresponding transmitted marker synchronizing signals. The refresh generators run asynchronously between marker synchronizing signals to select scan lines for refresh. The refresh generators each employ counters for counting a selected number M which is an integer having no factors in common with the number of scan lines of a frame to select scan lines for refresh which have different spatial positions in adjacent successive frames to avoid generating visible refresh artifacts.

Refresh system for digital signals with refresh cycle synchronization

A parallel-pipeline video signal processing system is disclosed which includes a statistical decoder, an arithmetic and logic unit and a pixel interpolator which operate in parallel under the control of sequencing circuitry to expand a compressed video signal. The video signal may have been developed using a variety of compression techniques including Huffman-type statistical encoding.

Processor for expanding a compressed video signal

A binary tree search system locates and outputs video data stored in a ROM, the data corresponding to received variable length uniquely encoded codewords. The data for each codeword is stored at a unique ROM address, each address corresponding to a tree leaf. Certain ROM locations not associated with complete codewords include a partial search address for the next search node, the remainder of the search address for each node comprising a bit of the serial received encoded data. When the received bits complete a codeword, the last received bit and the prior accessed ROM stored partial address form a pointer address to a tree leaf that accesses that ROM location containing the data corresponding to that codeword. Flags are generated by each accessed location to indicate whether or not a codeword has been found. If a codeword is found, the search is restarted at the tree root.

Growing community of inventors

Kingston, NJ, United States of America

Nicola J Fedele