Stmicroelectronics S.r.l.

Other

Nicola Del Gatto

Emanuele Confalonieri

Marco Sforzin

Massimiliano Mollichelli

Marco Ferrario

Carla Giuseppina Poidomani

Carlo Lisi

Vincenzo Dima

Massimiliano Scotti

Antonio Geraci

Nicola Rosito

Davide Cascone

Umberto Di Vincenzo

Alessandro Magnavacca

Paolo Turbanti

Carmelo Chiavetta

Claudio Nava

Roberto Versari

The circuit distributes a test signal applied to a pad of an electronic device that is enabled during test phases of the device and disabled during normal functioning. The circuit includes a 'master' buffer, one or more 'slave' buffers, one for each replicated pad, and an interconnection bus of the &#x201c;master&#x201d; and &#x201c;slave&#x201d; buffers. During a test phase, the &#x201c;master&#x201d; buffer replicates on the interconnection bus the test signal fed to a pad of the device, while the &#x201c;slave&#x201d; buffers convey to the various replica pads of the feed pad the signal present on the interconnection bus. During the normal operation of the device, the circuit remains disabled.

Circuit for distributing a test signal applied to a pad of an electronic device

A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.

Voltage regulator for the programming circuit of a memory cell

A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.

Memory device employing three-level cells and related methods of managing

A reading circuit for reading semiconductor memory cells, adapted to be coupled to at least one memory cell and to at least one reference cell through a respective bit line, the reading circuit including: a pre-charge circuit for pre-charging the bit lines to a predefined voltage during a pre-charge phase of a reading operation on the memory cell; a biasing circuit for applying a bias to a respective control terminal of the memory cell and of the reference cell in response to an enabling signal; and for each bit line, an evaluation circuit for evaluating an electric quantity developing on the bit line as a consequence of the bias during an evaluation phase of the reading operation on the memory cell, an information content of the memory cell being determined on the basis of the electric quantity that develops on the bit lines. The enabling signal is provided by the pre-charge circuit in response to an indication that the bit lines have reached the predefined voltage.

Reading circuit for semiconductor memory

A regulator for a digital-to-analog converter having in input a digital signal and suitable for providing an analog signal in output, the regulator including at least one pair of buffers having in input the digital signal and the outputs connected to a pair of circuit branches connected to the output of the regulator; each of the at least two circuit branches having at least one resistance. To at least one of the at least one pair of buffers a variable resistance is associated, and the regulator includes a circuit having in input the analog signal and adapted for measuring its waveform and acting on the variable resistance in response to its possible anomalous waveform compared to a desired waveform.

Regulator of a digital-to-analog converter and related converter

Method for configuring a voltage regulator

A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting the reaching of a threshold value by a current of each selected memory cell and of each reference cell, and means for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means for applying a controlled biasing current to the selected memory cells and to the at least one reference cell.

Memory device with a ramp-like voltage biasing structure based on a current generator

A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated with at least one respective column of said plurality. The semiconductor memory device further includes a bit line selection structure for selecting at least one among said bit lines and a voltage clamping circuit structure adapted to cause the clamping at a prescribed voltage of unselected bit lines adjacent and capacitively coupled to a selected bit line during a read operation.

Memory device

A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.

Memory device and method of operating the same with high rejection of the noise on the high-voltage supply line

A method and circuit for programming a multilevel memory of a flash EEPROM type having a matrix of cells grouped in memory words. The method provides for the simultaneous generation of a first programming voltage value and a second verify voltage value to bias word lines of the memory matrix during programming and verify operations, respectively, of the memory itself. A circuit implementing the above method is also provided.

Programming method of multilevel memories and corresponding circuit

A method for verifying an array cell of a memory device may include determining after each erase pulse or program pulse the threshold of a cell addressed through a selected array word-line and bit-line, by applying an identical voltage ramp to the selected array word-line and to the control gate of a reference cell, while biasing at a certain voltage deselected word-lines through distribution lines of the voltage generated by a charge pump generator. The method may further include temporarily decoupling the deselected word-lines from the distribution lines of the bias voltage for the duration of the voltage ramp.

Control of voltages during erase and re-program operations of memory cells

A method for management of the programming controls in a multilevel device is provided. During the control step cells are not controlled all together but they are conveniently selected in order to reduce the source resistance and consumption effect, but without penalizing change times.

Programming method for non volatile multilevel memory cells and corresponding programming circuit

A voltage regulator with quick response includes: an output terminal supplying a regulated voltage; and at least a first boost circuit, controlled for alternately accumulating a first charge in a first operating condition and supplying the first charge to the output terminal in a second operating condition. In addition, the first boost circuit is provided with a compensation stage supplying the output terminal with a second charge substantially equal to the first charge, when the first boost circuit is in the first operating condition.

Voltage regulator with very quick response

A circuit for biasing an input node of a sense amplifier is proposed. The circuit includes a voltage regulator for keeping the input node at a pre-set operative voltage during a sensing operation. The circuit further includes a pulling device for pulling the input node from a starting voltage towards a power supply voltage, the operative voltage being comprised between the starting voltage and the power supply voltage. The circuit also includes a control device for disabling the pulling device before the input node reaches the operative voltage.

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Torre del Greco, Italy

Nicola Del Gatto