Infineon Technologies Ag

Nicola DaDalt

Roberto Nonis

Edwin Thaller

Andrea Bevilacqua

Leonardo Lorenzon

Eva Tatschl-Unterberger

Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.

Multi-output phase detector

This disclosure relates to a divide-by-N frequency divider system and frequency dividing method. The system includes a ring oscillator having M stages, where M is an integer, and a zero mean current component coupled to one or more of the stages to provide a zero mean current flow path.

Frequency divider

Techniques and architectures corresponding to relaxation oscillators having output frequencies that are supply voltage independent are described. In a particular embodiment, an apparatus includes a relaxation oscillator having one or more capacitors and a compensation current circuit coupled to the relaxation oscillator. The compensation current circuit is configured to regulate current provided to the one or more capacitors of the relaxation oscillator in response to changes in a supply voltage provided to the compensation current circuit and to the relaxation oscillator.

Relaxation oscillator having a supply voltage independent output frequency

This disclosure relates to delay cells in a ring oscillator that include sub-cells having a gain that is a function of a variable control signal and sub-cells with a gain that is set by a fixed control signal.

Ring oscillator with constant gain

A phase locked loop is disclosed. One embodiment includes a phase comparator having two phase comparator inputs and a phase comparator output. A filter having a filter input and a filter output is provided, wherein the filter input is connected to the phase comparator output. A voltage controlled oscillator has a first oscillator input and an oscillator output. The first oscillator input is connected to the filter output and the oscillator output is connected to a first of the two phase comparator inputs. The oscillator has a second oscillator input. A coupling element is connected in parallel to the filter and arranged between the phase comparator output and the second oscillator input in such a way, that an output signal of the phase comparator is amplified and input to the second oscillator input.

Phase locked loop

Delta/sigma frequency discriminator () for converting a frequency (F) of an input signal into a digital output signal (C) comprising a frequency divider () which divides the input signal at a frequency dividing ratio which can be switched in dependence on the digital output signal (C), with at least one sampling register () which samples the divided input signal by means of a reference clock signal for generating the digital output signal (C), and with a dither circuit () which varies the clock period (T) of the reference clock signal so that interfering modulation tones in the signal spectrum of the digital output signal (C) are suppressed.

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Villach, Austria

Nicola DaDalt