Infineon Technologies Ag

Telecom Italia Lab S.p.a.

Nicola Da Dalt

Roberto Nonis

Peter Gregorius

Edwin Thaller

Christoph Sandner

Thomas Jackum

Davide Ponton

Werner Grollitsch

Thomas Santa

Roberto Quasso

Andrea Cristofoli

Giacolino Nervo

Peter Pridnig

Roberto Bonello

Paolo Mosca

Representative implementations of devices and techniques provide a spread spectrum clocking signal. In a frequency synthesizer, a sequence of values may be generated and used to modulate a frequency of an input signal to the frequency synthesizer.

Random spread spectrum modulation

Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.

Phase interpolator

Apparatuses and methods are provided where a predefined voltage may be applied in a feedback circuit of a voltage regulator, the feedback circuit coupling and output terminal with an adjust terminal of the voltage regulator.

Apparatus providing an output voltage

At least one implementation relates to a method that includes receiving a bias voltage provided by a low-dropout voltage regulator (LDO) error amplifier; supplying a feedback voltage to the LDO error amplifier; supplying a power signal to a load; and providing a control signal to enable or disable the load and enable or disable the LDO error amplifier.

LDO with distributed output device

Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.

Oscillator circuit

This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise.

Phase-locked loop (PLL)-based frequency synthesizer

An oscillator may output phased signals to a phase interpolator which is to generate an adjustable output clock signal having a phase offset relative to at least one of the phased signals received from the oscillator. A divider may then divide the frequency of the output signal generated by the phase interpolator by an integer factor.

Fractional frequency divider

A method and apparatus for supplying independently switched, regulated power to a plurality of loads is disclosed.

In one implementation, an apparatus includes a first input terminal configured to receive a bias voltage, the bias voltage received from a low-dropout voltage regulator (LDO) error amplifier, and a second input terminal configured to receive a supply voltage; a first output terminal configured to supply a feedback voltage, the feedback voltage supplied to the LDO error amplifier, and a second output terminal configured to supply regulated power to an associated load; a regulating portion configured to regulate power supplied to the associated load; and a switching portion configured to enable or disable the load from receiving the regulated power.

In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.

Circuit with noise shaper

In an embodiment, a circuit is provided comprising a multi-phase oscillator configured to output a plurality of output signals having the same frequency and different phase offsets. A feedback value is generated based on at least two of said output signals. A reference value is generated based on a reference clock and a predetermined value. The reference value and the feedback value are combined.

Circuit with multiphase oscillator

A method and a device are proposed for frequency synthesis by means of oscillator means, particularly a digitally controlled oscillator, which are capable of generating output frequencies out of a set of possible output frequencies. For the purpose of generating a desired frequency that is not included in the set of possible output frequencies, the oscillator means are driven by a control device in such a way that said oscillator means alternately generate at least two different output frequencies, out of the set of possible output frequencies, in such a way that the average value of the generated output frequencies over a time period is substantially the desired frequency.

Device and method for frequency synthesis

In a method for stabilizing a transfer function of a digital phase locked loop a random digital signal is fed into the phase locked loop. The phase locked loop comprises the transfer function and a phase locked loop gain which changes with time due to disturbances and the random digital signal comprises a predetermined variance. The transfer function depends from the phase locked loop gain. A cross correlation function is generated by cross correlating a signal of the phase locked loop with the random signal and an impulse response is estimated between the random signal and the signal of the phase locked loop by means of the cross correlation function and the predetermined variance of the random signal. The transfer function of the phase locked loop is set in dependence on the estimated impulse response.

Method and device for stabilizing a transfer function of a digital phase locked loop

A method and a device for generating a clock signal (F) are provided, wherein a digital phase difference signal (X) is formed depending on a phase difference between a reference clock signal (F) and a feedback signal (F) derived from the clock signal (F) and wherein the digital phase difference signal (X) is digitally filtered, in order to form a digital filtered phase difference signal (U). A digitally controlled oscillator () is activated by a digital control signal dependent on the digital filtered phase difference signal (U) to generate the clock signal (F). With a device of this kind clock signals with frequencies in the gigahertz range can be generated with a minimum of analog circuit parts.

Method and device for generating a clock signal using a phase difference signal and a feedback signal

A digital phase-locked loop with a digitally controlled oscillator is disclosed. The phase difference between a reference phase and a phase derived from the output phase of the oscillator is determined by a phase detector device and converted into a corresponding digital set value. The digital set value from the phase detector device is fed through a digital filter, to the digitally controlled oscillator, for the corresponding setting of the output phase thereof. By means of the above architecture any digital loop filter may be used.

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Villach, Austria

Nicola Da Dalt