U.S. Philips Corporation

Other

Nxp B.v.

Nico Frits Benschop

Adrianus Johannes Maria Denissen

Richard Petrus Kleihorst

Andre Krijn Nieuwland

Josephus Antonius Huisken

The subject matter hereof relates to error detection. Various example embodiments for error defection are disclosed. In an example method of error detection in a Module UnderTest (MUT), a parity signal representing the parity of an MUT output is compared to a parity signal representing the parity of an errorless MUT output. In an example system, an Actual Parity Generator provides a parity signal representing the parity of on MUT output, a State Parity Generator provides a parity signal representing the parity of an errorless MUT output, and a comparator compares these two parity signals.

Digital system and a method for error detection thereof

The invention relates to a multiplier for the multiplication of at least two figures in an original format. Each of said figures is fed to a first converter for conversion of each of said figures in the product of a first binary number representing a power of 2, and a second binary number representing a signed power of 3, the exponents of the powers of 2 of the concerning figures being fed to a first adder and the exponents of the powers of 3 of the concerning figures being fed to a second adder, whereby the combined respective outputs of the first adder and the second adder represent the multiplied value of said figures, and the resulting powers of 2 and 3 as available at the outputs of the first and second adder being fed to a second converter for conversion of the multiplied value into the original format.

Multiplier for the multiplication of at least two figures in an original

When the processing circuitry of a signal processor can handle data at a faster rate than the rate of arrival of signal units to be processed, the processor is able to execute a cycle of microcodes for each arriving signal unit. To generate the cycle, the signal processor contains base address reproducing means, for in each cycle reproducing a standard sequence of successive base addresses BA(i) (i=1 . . . N). The base address reproducing means feed microcode selecting means for selecting, in step with each base address and under control of signal data received from the processing circuitry, an associated microcode address MA(i) from a repertory of microcode addresses indicated by the base address BA(i). Selection is implemented by adding each base address BA(i) to an associated index IA(i), determined in dependence on signal data received from the processing circuitry. Usually, the indices IA(i) require fewer bits than the base addresses BA(i); the indices are determined in codependence of the base address, or of a signal identifying a class to which the base address belongs. The signal data is collected from the processing circuitry via a shift register.

Addressing scheme for microcode store in a signal processor

A MOS integrated logic circuit is described which comprises a plurality of groups (61, 63, 65, 67, 69) of combinatory logic elements. These groups form a cascade in that a data output of a preceding group is directly coupled to a data input of a next group within the cascade. During successive clock pulse phases the groups of combinatory logic elements are sampled in the sequence in which they are arranged in the cascade. Charging means provide the charge to be sampled, either by means of a precharge clock phase, or by virtue of being pull-up means.

Integrated logic circuit incorporating fast sample control

A device for multiplying two binary numbers in two's-complement notation having an array for forming bit-wise partial products and a further array for successively forming the result bits therefrom. The modules of the further array form either a full adder or a full subtractor under the control of a one-bit control signal. The negative sign of the most-significant bits of the factors can thus be taken into account. Devices of this kind can be linked in order to realize multiplications with higher precision, variation of the control signal signalling that only the device to which a most significant factor bit is applied takes into account a negative sign. A pipe line product-accumulator device is formed by construction in n-MOS dynamic logic circuits, with an inherent trigger function on the outputs of full adders/subtractors.

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Eindhoven, Netherlands

Nico Frits Benschop