Fairchild Semiconductor Corporation

Nickole Gagne

Kenneth Patrick Snowdon

Steven M Macaluso

Gregory A Maher

Julie Lynn Stultz

Christian Klein

Roy L Yarbrough

Tyler Daigle

Oscar W Freitas

James B Boomer

Paul Fournier

Jouni Mika Kalervo Vuorinen

Derek Richardson

Daniel Gagne

Jani Kauppinen

An apparatus comprises an integrated circuit (IC) comprising an external IC connection, an IC substrate connection, a voltage clamp circuit and an under voltage circuit. The voltage of the IC substrate connection is set to a first voltage when a voltage of the external connection of the IC is within a normal operating voltage range. The voltage clamp circuit is configured to clamp the voltage supply of one or more circuits internal to the IC to within a normal operating voltage range when the voltage of the external IC connection exceeds the normal operating voltage range. The under voltage circuit is communicatively coupled to the clamp circuit and configured to set the voltage of the substrate to a second voltage when the voltage at the external IC connection of the IC is less than zero volts.

Under voltage tolerant clamp

Method and apparatus, among other things, are provided for detecting a charger type. In an example, a method to classify a potential charger coupled to a port of an electronic device can include detecting the potential charger coupled to a USB-compatible port of the electronic device, applying a pull-down current to first and second data lines of the USB-compatible port to provide a first test voltage on each of the first and second data lines, and executing a primary detection process of a USB Battery Charging 1.2 Compliance Plan if the first test voltage on each of the first and second data lines is not between a first threshold and a second threshold using the pull-down current.

Charger detection with proprietary charger support

This document discusses, among other things, a control circuit, such as a translator circuit, configured to reduce voltage stress of first and second transistors when a first voltage received by the first transistor exceeds a voltage rating of at least one of the first or second transistors.

Translator including overstress protection

Apparatus and methods for a protective multiplexer, among other things, are provided. In an example, a protective multiplexer circuit can include a first switch that in a first state can be configured to couple an input of a power supply to at least one of first or second signal nodes of a passgate when a first voltage of the at least one of the first or second signal nodes is below a first limit voltage.

Protective multiplexer

A power supply system is provided that provides voltage clamping capabilities to provide over voltage protection to circuit elements and circuit systems. The power supply includes isolation mechanisms that generate a regulated power supply that is independent of an input power source. Voltage addition/multiplication techniques may be utilized to generate a reference voltage, from the regulated power supply, that is capable of setting a maximum voltage on a clamped power supply. The power supply system may operate without input from other circuits/systems associated with an integrated circuit.

Self-sustaining, high voltage tolerant power supply

This document discloses, among other things, a voltage clamp circuit where an output voltage equals an input voltage for at least a portion of a first range of input voltages, and where the output voltage is less than the input voltage for at least a portion of a second range of input voltages.

High voltage clamp circuit

In one general aspect, an apparatus including a first voltage rail, and a second voltage rail. The apparatus includes a first P-type metal-oxide-semiconductor field effect transistor (MOSFET) PMOS device between the first voltage rail and the second voltage rail where the first PMOS device is configured to electrically couple the first voltage rail to the second voltage rail in response to the first PMOS device being activated. The apparatus can also include a second PMOS device configured to provide a charge pump voltage produced by a charge pump device to the second voltage rail in response to the second PMOS device being activated and the first PMOS device being deactivated. The apparatus can also include a pass gate, and a driver circuit coupled to the pass gate and configured to operate based on a voltage of the second voltage rail.

Methods and apparatus for voltage selection for a MOSFET switch device

In one general aspect, an apparatus can include a complementary switch circuit including a first portion and a second portion, and a first driver circuit coupled to the first portion of the complementary switch circuit. The apparatus can include a positive charge pump device coupled to the first driver, and a second driver circuit coupled to the second portion of the complementary switch circuit. The apparatus can also include a negative charge pump device coupled to the second driver circuit.

Methods and apparatus related to an improved complementary MOSFET switch

This document discusses methods and apparatus for preventing or reducing sub-threshold pass gate leakage. In an example, an apparatus can include a pass gate configured to electrically couple a first node with a second node in a first state and to electrically isolate the first node from the second node in a second state, control logic configured to control the pass gate, wherein the control logic includes a supply rail, and an over-voltage circuit configured to compare voltages received at a plurality of input nodes and to couple an output to an input node a highest voltage. In an example, the output of over-voltage circuit can be selectively coupled to the supply rail.

Pass gate off isolation

An integrated circuit (IC) comprises a transistor circuit and a voltage generator circuit. The voltage generator circuit is configured to generate an activation voltage for the transistor circuit using an output voltage at an output of the transistor circuit, and maintain a gate-source voltage (V) of the transistor circuit at a substantially constant voltage above the output voltage when a magnitude of the generated activation voltage is less than a device voltage rating of the IC and when the magnitude of the generated activation voltage meets or exceeds the device voltage rating of the IC.

Constant VGS charge pump for load switch applications

This document discusses, among other things, a compensation circuit configured to modulate a control voltage of a switch over a range of ambient temperatures during a conduction state of the switch to maintain a specified resistance between first and second nodes of the switch. The compensation circuit can include a temperature-insensitive resistor configured to provide a sense current, a current mirror configured to provide a mirror current using the sense current, and a temperature-sensitive resistor configured to provide the control voltage using the mirror current.

Stable ON-resistance switch circuit

This application discusses, among other things, switch circuit apparatus having power down protection and not requiring power up sequencing. An apparatus embodiment can include a first supply node coupled to a first input of a level shifting circuit via a protection circuit, a second supply node coupled to a second input of the level shifting circuit via a single pull-up transistor, and a switch including a control input, a first node, and a second node controllably isolated from the first node, wherein the control input is coupled to the level shifting circuit. The first and second inputs of the level shifting circuit can be coupled via a rectifier, and the protection circuit can be configured to power the first and second supply nodes to controllably isolate the first and second nodes from each other when a voltage of one of the first or second nodes exceeds a threshold.

Charge pump switch power down protection

A polysilicon resistor fuse has an elongated bow-tie body that is wider at the opposite ends relative to a narrow central portion. The opposite ends of the body of the fuse have high concentrations of N-type dopants to make them low resistance contacts. The upper portion of the central body has a graded concentration of N-type dopants that decreases in a direction from the top surface toward the middle of the body between the opposite surfaces. The lower central portion of the body is lightly doped with P-type dopants. The central N-type region is a resistive region.

Polysilicon drift fuse

An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.

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Saco, ME, United States of America

Nickole Gagne