International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Nickolaus J Gruendler

Bhyrav M Mutnury

Terence K Rodrigues

Michael Jay Shapiro

Jimmy Grant Foster, Sr

Bruce James Wilkie

Matthew R Archibald

Jerrod Kimmel Buterbaugh

Tae Hong Kim

Paul Marian Harvey

Sang Y Lee

Suzanne M Michelich, Iii

Jacques B Taylor

Methods, apparatus, and products for optimizing delivery of regulated power from a voltage regulator to an electrical component, operation of the voltage regulator controlled by a service processor, the voltage regulator including a number of phases, each phase rated to deliver a different maximum power to the electrical component, where optimizing delivery of regulated power includes determining, by the service processor, the present power requirements of the electrical component, and enabling, by the service processor, one or more phases of the voltage regulator in dependence upon the present power requirements of the electrical component.

Optimizing delivery of regulated power from a voltage regulator to an electrical component

One or more decoupling capacitors are coupled to a low inductance mount that is connected to the bottom layer of a printed circuit board (PCB) on which a semiconductor module is mounted. The low inductance mount includes a magnetic planar structure with vias that are coupled to the one or more decoupling capacitors and to like vias positioned on the PCB.

Noise suppressor for semiconductor packages

Establishing a power profile of power consuming components of computer system configurations for generating electrical ratings, beginning with a default, limited configuration of a computer system and continuing for a number of configurations of the computer system, each configuration including additional power consuming components not included in a previous configuration, where establishing a power profile includes: measuring, for a present configuration, power consumption of the computer system; calculating, in dependence upon the measured power consumption for the present configuration, an estimated power rating for the one or more additional power consuming components; and recording, in a power profile, estimated power ratings for the additional power consuming components, where the number of configurations of the computer system for which power consumption is measured is less than the number of possible configurations of the computer system.

Establishing a power profile for generating electrical ratings

A receiver circuit detects an eye margin within a differential signal having a true component and a complement component. A transmitter circuit adjusts a phase between the true component and the complement component of the differential signal, based on the eye margin, to improve the eye margin. Improving the eye margin results from a reduction in common mode noise within the differential signal.

Common mode noise reduction within differential signal

An apparatus comprises a multi-layer printed circuit board having at least three conductor layers, a dielectric material layer between each of the conductor layers, and a laminate capacitor stack arranged transversely through the printed circuit board. The laminate capacitor stack comprises: (a) a plurality of conducting patches including a patch in a plurality of the conductor layers, wherein the plurality of patches are aligned in a stack with the dielectric material filling the space between adjacent patches; (b) a first conducting via interconnecting each patch in a first subset of the plurality of patches, wherein the first subset of the plurality of patches are coupled to one of the conductor layers that is at ground potential; and (c) a second conducting via interconnecting each patch in a second subset of the plurality of patches, wherein the second subset of the plurality of patches are coupled to one of the conductor layers that is at power potential, wherein the patches in the first subset are disposed in an alternating pattern with the patches in the second subset.

Laminate capacitor stack inside a printed circuit board for electromagnetic compatibility capacitance

Fault injection in dynamic random access memory ('DRAM') modules for performing built-in self-tests ('BISTs') including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault characterized by a fault type; writing data by the memory controller through a data bus to the DRAM modules, the data identifying a particular DRAM module; and responsive to receiving the data, injecting, by the particular DRAM module, the fault characterized by the fault type into the one or more signal lines of the particular DRAM module.

Growing community of inventors

Manor, TX, United States of America

Nickolaus J Gruendler