Xilinx, Inc.

Nicholas Trank

Chandrasekhar S Thyamagondlu

Tao Yu

Chiranjeevi Sirandas

A direct memory access (DMA) system includes a plurality of read circuits and a switch coupled to a plurality of data port controllers configured to communicate with one or more data processing systems. The DMA system includes a read scheduler circuit coupled to the plurality of read circuits and the switch. The read scheduler circuit is configured to receive read requests from the plurality of read circuits, request allocation of entries of a data memory for the read requests, and submit the read requests to the one more data processing systems via the switch. The DMA system includes a read reassembly circuit coupled to the plurality of read circuits, the switch, and the read scheduler circuit. The read reassembly circuit is configured to reorder read completion data received from the switch for the read requests and provide read completion data, as reordered, to the plurality of read circuits.

Direct memory access system with read reassembly circuit

Descriptor fetch for a direct memory access system includes, in response to receiving a first data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors. The plurality of descriptors specify different buffer sizes. In response to processing each data packet, selectively replenishing the plurality of fetched descriptors to the specified number of prefetched descriptors.

Variable buffer size descriptor fetching for a multi-queue direct memory access system

Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.

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San Francisco, CA, United States of America

Nicholas Trank