Micron Technology Incorporated

Ovonyx Memory Technology, LLC

Numem Inc.

Intel Corporation

Other

Avago Technologies General IP (singapore) Pte. Ltd.

Nicholas T Hendrickson

Gerald J Barkley

Eric Hall

Doug Smith

Jack Guedj

Kerry Dean Tedrow

Robert Melcher

Anthony R Cabrera

Aswin Thiruvengadam

Xinwei Guo

Yihua Zhang

Rich Fackenthal

Arvind Muralidharan

Matthew T Hendrickson

James I Esteves

Matthew Cole Hendrickson

Embodiments of the present disclosure relate to operations related to extracting subsections of an obtained image corresponding to an environment. The operations may further include, determining one or more gradients of pixel intensities corresponding to the subsections of the obtained image. Further, determining one or more vectors based on a frequency corresponding to the one or more gradients of pixel intensities corresponding to the subsections corresponding to the obtained image. The operations may further include classifying one or more characteristics corresponding to the obtained image using one or more machine learning models and detecting a presence of one or more safety triggers in the environment based on the one or more determined vectors corresponding to the one or more subsections of the obtained image. Further, the operations may include automatically deploying a safety indicator based on the detecting the presence of the one or more safety triggers in the environment.

Systems and methods for automatic spotting and safety indicator deployment

An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Adaptive memory management and control circuitry

Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Smart compute resistive memory

An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Apparatus and methods to provide power management for memory devices

An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses are also provided.

An apparatus for storing data in a magnetic random access memory (MRAM) is provided. The MRAM may store data in one or more resistance-based memory cells and may include a plurality of comparators to compare a voltage generated based on the resistance-based memory cells to a reference voltage to determine a stored logic state. In some implementations, the reference voltage may be generated by a plurality resistance-based memory cells. The reference voltage may be adjusted higher or lower by storing different logic states within the resistance-based memory cells.

Reference voltage generator for resistive memory array

Memory devices, such as MRAM devices, are described that comprise memory elements for storing data and configuration logic for programming memory elements using a two phase boost. The memory devices perform the two phase boosting to program anti-parallel data values during a first programming phase and to program parallel data values during a second programming phase that is subsequent to the first programming phase. The voltage boost is provided by a high percentage of memory elements in a memory device by simultaneously transitioning the source line of the memory elements from a reference voltage to a source voltage during the first programming phase to effectively double the activation voltage for gates of transistors in the memory elements to program anti-parallel data values. Methods are also described for programming memory elements using a two phase boost.

Programming memory elements using two phase boost

Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic level of a command signal line to generate a command signal to control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal indicates that the operation is not being performed, and having a particular logic level when the output signal indicates that the operation is being performed. Integrated circuit devices include a command signal management circuit to provide a logic level of a particular command signal to control circuitry of the integrated circuit device when control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the control signals indicate a desire to block the particular command signal.

Command signal management in integrated circuit devices

Methods of operating a memory device include performing a first memory operation having an associated timing requirement; after completing the first memory operation, determining whether a timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds a length of time to perform a particular portion of a second memory operation; and performing the particular portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the particular portion of the second memory operation.

Operation management in a memory device

Apparatuses, integrated circuits, and methods are disclosed for testmode security systems. In one such example apparatus, a data storage is configured to store data. A testmode security system is configured to allow a user to access one or more testmodes of the apparatus at least partially responsive to the data storage not storing sensitive data and disallow the user from accessing the one or more testmodes of the apparatus at least partially responsive to the data storage storing sensitive data.

Growing community of inventors

Folsom, CA, United States of America

Nicholas T Hendrickson