International Business Machines Corporation

Nicholas Steven Rolfe

Steven R Carlough

Gary A Van Huben

Susan M Eickhoff

Markus Cebulla

Logan I Friedman

Walter Pietschmann

Patrick James Meaney

Stephen J Powell

Brad William Michael

John Samuel Liberty

A memory controller receives, via a first interface, a first read request requesting a requested data granule. Based on receipt of the first read request, the memory controller transmits, via a second interface, a second read request to initiate access of the requested data granule from a system memory. Based on a determination to schedule accelerated data delivery and receipt by the memory controller of a data scheduling indication that indicates a timing of future delivery of the requested data granule, the memory controller requests, prior to receipt of the requested data granule, permission to transmit the requested data granule on the system interconnect fabric. Based on receipt of the requested data granule at the indicated timing and a grant of the permission to transmit, the memory controller initiates transmission of the requested data granule on the system interconnect fabric and transmits an error indication for the requested data granule.

Reduced system memory latency via a variable latency interface

A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.

Register access in a distributed memory buffer system

A method, apparatus and system testing a plurality of semiconductor chips in a distributed memory buffer system is provided. Embodiments of the present invention recognize improvements to testing signals through the chip substrate and motherboard. This invention overloads the shared broadcast bus by using it for test purposes rather than its normal mainline function. One of the main components of this invention is the A/C chip. In test mode, the AC chip converts JTAG commands into an internal test format and sends test data over the shared broadcast bus. Each data chip determines whether the scan data is for itself or if it should ignore it. The corresponding data chip then processes the data, and if necessary sends return data back to the address and command chip, where it is converted back into JTAG format and can be seen by the tester.

JTAG support over a broadcast bus in a distributed memory buffer system

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Hyde Park, NY, United States of America

Nicholas Steven Rolfe