Texas Instruments Corporation

Nicholas Stephen Dellas

Brian Goodlin

Ricky A Jackson

Dong Seup Lee

Neng Jiang

Ting-Ta Yen

Maciej Blasiak

Qhalid R S Fareed

Scott Robert Summerfelt

Rick L Wise

Stuart M Jacobsen

Naveen Tipirneni

Qhalid Fareed

Elizabeth Costner Stewart

Django Trombley

Iouri N Mirgorodski

Joel Soman

Maria Wang

Tatsuya Tominari

Andinet Tefera Desalegn

A method includes depositing a first epitaxial layer of an aluminum gallium nitride (AlGaN) material onto a preliminary substrate and polishing the first layer's surface. Ions are implanted beneath the surface, which is bonded to a seed insulating substrate. Annealing is performed, resulting in second epitaxial layer on preliminary substrate and third epitaxial layer on seed insulating substrate. Third layer's surface is polished to obtain a seed wafer. In some implementations, a fourth epitaxial layer of a second AlGaN material is deposited onto surface of third layer. Fourth layer's surface is polished, and ions are implanted beneath the surface, which is bonded to a product insulating substrate. Annealing is performed, resulting in fifth epitaxial layer on seed insulating substrate and sixth epitaxial layer on product insulating substrate. The sixth layer can be used to obtain an AlGaN product, and the fifth layer can be reused to fabricate additional AlGaN products.

Technique for GaN epitaxy on insulating substrates

A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.

P type gallium nitride conformal epitaxial structure over thick buffer layer

Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.

Electronic device with gallium nitride transistors and method of making same

In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

Transistor with buffer structure having carbon doped profile

A method of fabricating a gate stack for a power transistor device includes thermally oxidizing a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer of an oxide material that is &#x3e;5 A thick. A second dielectric layer being silicon nitride or silicon oxynitride is deposited on the first dielectric layer. A metal gate electrode is formed on the second dielectric layer.

Method of making a high power transistor with gate oxide barriers

A micromechanical system (MEMS) acoustic wave resonator is formed on a base substrate. A piezoelectric member is mounted on the base substrate. The piezoelectric member has a first electrode covering a first surface of the piezoelectric member and a second electrode covering a second surface of the piezoelectric member opposite the first electrode, the second electrode being bounded by a perimeter edge. A first guard ring is positioned on the second electrode spaced apart from the perimeter edge of the second electrode.

Buk acoustic wave resonator with guard rings having recessed space from electrode edge and periodic designs

A method for creating a double Bragg mirror is provided. The method comprises providing a wafer having a plurality of bulk acoustic wave (BAW) devices at an intermediate stage of manufacturing. A first dielectric layer is deposited over the wafer. A plurality of as-deposited thicknesses of the dielectric layer are determined, each as-deposited thickness corresponding to one BAW device from the plurality of BAW devices. A corresponding trimmed dielectric layer over each of the BAW devices is formed by removing a portion of the dielectric layer over each of the BAW devices, with a thickness of the removed portion determined from a corresponding as-deposited thickness and a target thickness. A Bragg acoustic reflector that includes the corresponding trimmed dielectric layer is formed over each of the BAW devices.

Method for creating double bragg mirror for tight frequency reference control

In described examples of a micromechanical system (MEMS), a rigid cantilevered platform is formed on a base substrate. The cantilevered platform is anchored to the base substrate by only a single anchor point. A MEMS resonator is formed on the cantilevered platform.

Bulk acoustic wave resonator on a stress isolated platform

A method of tuning the resonant frequency of embedded bulk acoustic resonators during manufacturing of an integrated circuit. The rate of change in the resonant frequency of BAWs vs rate of change in top electrode thickness is determined and used to tune the resonant frequency of embedded bulk acoustic resonators during integrated circuit manufacturing.

Method to reduce frequency distribution of bulk acoustic wave resonators during manufacturing

A microelectronic device contains a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800&#xb0; C. to 820&#xb0; C.

Low-stress low-hydrogen LPCVD silicon nitride

Method of forming a termination angle in a titanium tungsten layer include providing a titanium tungsten layer and applying a photo resist material to the titanium tungsten layer. The photo resist material is exposed under a defocus condition to generate a resist mask, wherein an edge of the exposed photo resist material corresponds to the sloped termination. The titanium tungsten layer is etched with an etching material, wherein the etching material at least partially etches the photo resist material exposed under the defocused condition, and wherein the etching results in the sloped termination in the titanium tungsten layer.

Devices with specific termination angles in titanium tungsten layers and methods for fabricating the same

The dominant frequency of a solidly mounted resonator () is substantially increased by reducing the thickness of each layer of each Bragg acoustic reflector () to have a thickness than is substantially equal to one-quarter of the wavelength of a frequency that is a higher harmonic resonant frequency of the fundamental resonant frequency of the solidly mounted resonator ().

Temperature compensated bulk acoustic wave resonator with a high coupling coefficient

A semiconductor device has a substrate with a semiconductor material. The semiconductor device includes a field effect transistor in and on the semiconductor material. The field effect transistor has a gate dielectric layer over the semiconductor material of the semiconductor device, and a gate over the gate dielectric layer. The gate dielectric layer includes a layer of nitrogen-rich silicon nitride immediately over the region for the channel, and under the gate.

Silicon nitride process for reduction of threshold shift

A method of fabricating a sloped termination of a molybdenum layer includes providing the molybdenum layer and applying a photo resist material to the molybdenum layer. The photo resist material is exposed under a defocus condition to generate a resist mask having an edge portion. The molybdenum layer is etched at least at the edge portion of the resist mask to result in a sloped termination of the molybdenum layer.

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Dallas, TX, United States of America

Nicholas Stephen Dellas