Apple Inc.

Nicholas Seroff

Anthony Fai

Nir Jacob Wakrat

Jahan C Minoo

Systems and methods are provided for obtaining and using nonvolatile memory ('NVM') health information. Health information can include a variety of information associated with the performance and reliability of portions of an NVM device, such as the number of errors detected in a portion of NVM or the amount of time required to read from or program a portion of nonvolatile memory. During operation, address specific health information may be stored passively on a host device and provided as part of a command to a memory controller. The memory controller may extract the health information from the command and use the information to execute access requests. After an access request is completed, the memory controller can update the health information and transmit the information back to the host device.

Systems and methods for obtaining and using nonvolatile memory health information

Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

Systems and methods for stacked semiconductor memory devices

Microphone assemblies may be provided that have microelectromechanical systems microphones and associated application-specific integrated circuits mounted to printed circuit boards. The application-specific integrated circuits may contain amplifier circuitry for amplifying microphone signals from the microphone. One or more though-silicon vias may be formed in the application-specific integrated circuit that serve as an acoustic port through which sound may pass. The application-specific integrated circuit may be embedded in the printed circuit board and the microphone may be mounted to the upper surface of the printed circuit board, the application-specific integrated circuit and microphone may be stacked on the upper surface of the printed circuit board, or the microphone and application-specific integrated circuit may be mounted to the printed circuit board so that the microphone is received within an opening in the printed circuit board.

Microphone assemblies with through-silicon vias

Systems and methods are provided for improved communications in a nonvolatile memory ('NVM') system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.

Systems and methods for improved communications in a nonvolatile memory system

This document generally describes systems, devices, methods, and techniques for obtaining debug information from a memory device. Debug information can include a variety of information associated with a memory device that can be used for debugging the device, such as a sequence of operations performed by the memory device and information regarding errors that have occurred (e.g., type of error, component of memory device associated with error). A memory device can be instructed by a host to obtain and provide debug information to the host. A memory device can be configured to obtain particular debug information using a variety of features, such as triggers. For instance, a memory device can use a trigger to collect debug information related to failed erase operations.

Obtaining debug information from a flash memory device

In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.

Debugging a memory subsystem

Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget.

Asynchronous management of access requests to control power consumption

Systems and methods for providing early hinting to nonvolatile memory charge pumps are disclosed. Charge pumps associated with one or more nonvolatile memory dies can be proactively activated based on a determination that a command queue of access requests contains at least a threshold number of consecutive access requests of the same type. Based on analysis of the command queue, the memory controller can transmit an early hint command to a nonvolatile memory die to proactively activate its charge pump to provide a voltage suitable for executing the consecutive access requests of the same type.

Systems and methods for providing early hinting to nonvolatile memory charge pumps

In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.

Controller interface providing improved data reliability

In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory accessible by a controller of the memory device; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, firmware from a host device, wherein the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the firmware from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained through communication with the memory controller of the memory device.

Booting a memory device from a host

This document generally describes systems, devices, methods, and techniques for variably controlling impedance for a memory device where multiple NVM units (e.g., NVM dies) are accessible over a shared bus. Impedance can be varied using switches that are configured to switch between a NVM unit and an impedance terminal. Switches can be adjusted during operation of a memory device so that a memory controller is connected over a shared bus to a selected single NVM unit and one or more impedance terminals. Impedance terminals can be configured to provide a relatively small load (a smaller load than an NVM unit) that is impedance matched (alone or in combination with other impedance terminals and/or a NVM unit) with a source impedance on a shared bus that is provided by a memory controller.

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Los Gatos, CA, United States of America

Nicholas Seroff