Primarion Corporation

Infineon Technologies Austria Ag

Trw Limited

Nicholas Robert Steffen

Benjamim Tang

Robert T Carroll

Keith Nelson Bassett

Tim Ng

Kenneth A Ostrom

Scott Wilson Southwell

Benjamin Tang

Richard Pierson

Allen J Bronowicki

William B Pohlman

Clifford Duong

Timothy M Ng

George R Dvorsky

Ken Ostrom

Theodore W Nye

Richard E Wyse

Claude I Kansaku

Cliff Duong

A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

PLL/DLL dual loop data synchronization

Disclosed is a power regulator for providing precisely regulated power to a microelectronic device such as a microprocessor. Improved power regulation is accomplished by optimizing the power efficiency of the power regulator. In particular, in a multiphase system, the number of active phases is increased or decreased to achieve optimum power efficiency. The multiphase voltage regulator adapts the operating mode to maximize efficiency as the load current demand of the load device changes by adjusting the number of active phases to maximize efficiency. The total value of current provided by the regulator and the total number of active phases is determined, the total number of active phases is compared with the number of active phases required to provide the total value of current at maximum efficiency; and the number of active phases is adjusted to provide the total value of current at maximum efficiency. A current sense circuit senses the current at each phase, a summing circuit coupled to the output of the current sense circuit provides the total current value of all the measured phases, a circuit coupled to the output of the summing circuit provides the time averaged total current value to a threshold detecting circuit that determines the number of phases at which the voltage regulator should be operating for maximum efficiency, and a circuit for comparing the number of phases that are operating to the number of phases at which the voltage regulator should be operating adjusts the number of active phases to the number of phases at which the voltage regulator should be operating for maximum efficiency.

Multiphase power regulator with load adaptive phase control

A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill level indicator is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL, which represents a fill level of a FIFO. A granular FIFO fill level indicator of the DLL provides input to the phase shifter to adjust the frequency of the PLL accordingly. Thus, the frequency of the data input rate can be controlled and a constant fill level of the FIFO can be maintained. A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator

A method, apparatus, and system for providing operating power and transient suppression power to a microelectronic device are disclosed. The system includes a primary regulator to supply nominal operating power and to respond to relatively slow transient events and a transient suppression regulator to respond to fast transient power events. The system also includes a sense circuit to detect when a transient event occurs and to send a signal to the transient suppression regulator to supply or sink current to the load in response to a sensed transient power event.

Method and apparatus for providing wideband power regulation to a microelectronic device

A method, apparatus, and system for routing signals in a microelectronic device are disclosed. The system includes a plurality of chip components, such as transient suppression regulators, that are configured to include a transmission path that is routed through the chip component for transmission of any signal, for example, a signal from a communication bus of the microelectronic device.

Power, ground, and routing scheme for a microprocessor power regulator

A system is provided for supplying current to a dynamic load subject to transient current requirements. A sense unit coupled to the dynamic load is configured to sense the rate of change of supply current required by the dynamic load during a transient event. A current source coupled to the sense unit is configured to supply a current pulse to the dynamic load in response to the sense unit determining that the rate of change of supply current (di/dt) exceeds a predetermined threshold. The current pulse preferably has a shape characterized by a first region and a second region subsequent to the second region, wherein the first region includes a first boost current which exceeds the transient current requirement, and wherein the second region includes a second boost current which is less than the transient current requirement. More generally, a wideband transient suppression system is provided for controlling a wide spectrum of transients. The wideband system includes a primary regulator configured to compensate for low frequency transients, and a secondary regulator configured to provide short-term compensation current to the dynamic load until the relatively slow primary regulator can accommodate the transient event. The secondary regulator includes two major functional blocks: a close-loop voltage-sensing compensation circuit configured to compensate for transients falling within a mid-range frequency range, and an open-loop di/dt-sensing compensation circuit configured to compensate for transients falling within a high-frequency range.

Methods and apparatus for open-loop enhanced control of power supply transients

A serial bus control method, apparatus, and system for transmitting signals between a master controller and a slave controller associated with a power regulator are disclosed. The serial bus control scheme allows for information to be written to or read from individual regulators or be written to read from all regulators that are coupled to the master controller.

Serial bus control method and apparatus for a microelectronic power regulation system

Modular control patches including assemblies of sensors and actuators are provided to impart or control vibration of foundation members such as struts in aerospace apparatus. Local digital electronic control means is associated with each control patch assembly. Programmable digital compensators in the control permits operation of the patches to be remotely varied. Patches are attached mechanically or by chemical bonding to the outside of the struts so that the electronics can be selectively removed and replaced. The patch being the sensors and actuators may also be attached or embedded with a composite structure.

Growing community of inventors

Redondo Beach, CA, United States of America

Nicholas Robert Steffen