Motorola Corporation

Cicada Semiconductor Corporation

Lucent Technologies Inc.

Crystal Semiconductor Corporation

Other

Alcatel-lucent USA Inc.

Vitesse Semiconductor Corporation

Nicholas R Van Bavel

Tim A Williams

Shawn R McCaslin

John James Paulos

James David Barnette

Mandeep Singh Chadha

Jeffrey William Scott

Eric J Swanson

Andrew W Krone

Marty Lynn Pflum

Charles D Thompson

Zhuo Fu

Salvador R Bernadas

Pradeep Katikaneni

Eric James Wyers

A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that receives the plurality of intermediate samples via one delay line of single bits and select one thereof, thereby providing an output sample that corresponds to a phase of the oscillator.

Resampler for a bit pump and method of resampling a signal associated therewith

Transformerless ethernet controller. A method for isolating an ethernet controller, having a transceiver associated therewith, from a twisted wire transmission line is provided. The power supply of the transceiver is DC isolated from system power supply. The data side of the ethernet controller is DC isolated from the transceiver for both transmit and receive data. The transceiver is directly connected to the transmission line with no DC isolation.

Transformerless ethernet controller

A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that selects one of the plurality of intermediate samples thereby providing an output sample that corresponds to a phase of an oscillator associated with the bit pump.

A filter circuit, method of configuring the filter circuit, and a bit pump and transceiver employing the circuit and method. In one embodiment, the filter circuit includes a noise prediction equalizer that generates a noise prediction equalizer coefficient during activation of the bit pump to reduce an intersymbol interference associated with a receive signal propagating along a receive path of the bit pump. The filter circuit also includes a decision feedback equalizer that generates a decision feedback equalizer coefficient during the activation of the bit pump to reduce the intersymbol interference associated with the receive signal. The noise prediction equalizer is concatenated with the decision feedback equalizer during showtime of the bit pump to form a precoder associated with a transmit path of the bit pump.

Filter circuit for a bit pump and method of configuring the same

Output driver for high speed Ethernet transceiver. A transmission line driver is disclosed for driving a transmission line in a first operating mode and in a second operating mode. The first and second operating modes operate substantially exclusive of each other. A current driver is provided for driving the transmission line in the first operating mode from a first data generator and at a first output voltage. A voltage driver is provided for driving the transmission line in the second operating mode from a second data generator at a second output voltage through a load, such that the current driver and the voltage driver operate independent of each other.

Output driver for high speed Ethernet transceiver

Reduced GMII with internal timing compensation A data interface between first and second integrated circuits. An internal clock signal is generated internal to the first integrated circuit and operates in a first frequency. A data generator is provided for generating data from at least one edge of the internal clock for transmission to the second integrated circuit. a first delay block internal to the first integrated circuit delays the internal clock for a predetermined duration of time less than one-half clock cycle of said internal clock to provide a first delayed clock. The second integrated circuit is then operable to receive the transmitted first delayed clock and utilize the transmitted first delayed clock to sample the received data generated by the data generator.

Reduced GMII with internal timing compensation

A pad calibration circuit with on-chip resistor. An integrated circuit with an impedance terminated output terminal is disclosed. A source is provided for sourcing current to the output terminal of the integrated circuit, which output terminal interfaces with a load having a finite impedance associated therewith. An on-chip source impedance is disposed internal to the integrated circuit and between the source and the output terminal to define the input impedance of the output terminal.

Pad calibration circuit with on-chip resistor

A PSD template for an HDSL2 transmission system includes three regions, a full-duplex region for both upstream and downstream transmission, and two half-duplex regions, a first duplex region for containing substantially upstream power and a half-duplex region for containing substantially downstream power.

Transmission spectra for HDSL2 transmission

A low precision Finite Impulse Response filter (FIR) is provided for filtering in a digital interpolation operation. The interpolation operation is comprised of two steps, a sampling rate conversion operation for interspersing zeroes between samples in an input sequence and a filtering step of filtering out images that result from this operation. The filtering operation utilizes a FIR filter that utilizes a low precision set of filter coefficients that are selected to tune the frequency response such that the low end frequency response including the pass band, the transition band, and the portion of the stop band immediately after the transition band provides a response equivalent to that commensurate with substantially higher precision FIR filter coefficients. A second, low pass filter section is provided for filtering the high frequency image energy at the output of the FIR filter to provide an overall filter response commensurate to that utilizing substantially higher precision FIR coefficients. The FIR filter coefficients utilized are restricted to the set of {-1, 0, +1} such that an arithmetic-free realization is provided wherein data is stored in a random access memory (68), with the non-zero coefficients for any interpolator output limited to a predetermined number. This predetermined number equals the maximum clock rate divided by the output sampling frequency. For each interpolator output, addresses of the associated data are stored in a ROM (72), which is operable to sequentially generate the addresses for accessing of data from a RAM (68). The sign is then changed, depending upon a sign change bit in the ROM (72), and then accumulated in an output accumulator (82). After all data is accessed from the RAM (68) for a given interpolator output, the accumulator (82) provides this output to the delta-sigma converter.

Arithmetic-free digital interpolation filter architecture

A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta. coefficient is stored in a block (16) and is generated during a calibration cycle by a .delta. processor (39). The .delta. processor (39) receives the output of the compensation circuit (14) and the digital output from the summing junction (36) when the calibration multiplexer (10) sets the input to zero. A control circuit (40) controls the overall operation, with the calibration operation initiated in response to either an external signal on a line (30) or an internally generated signal. After calibration, the value of the .delta. coefficient is frozen and the calibration multiplexer (10) selects the analog input.

Method and apparatus for calibrating a multi-bit delta-sigma modular

A transient-error free interpolating decimator utilizes only two comb filters. The decimator has an integrator circuit, which receives a digitized signal at a first clock rate, and a differentiator circuit. The differentiator includes first and second comb filters for down converting the digital signal at the first clock rate to a second clock rate, and for providing sample points at first and second outputs; the differentiator circuit and the integrator circuit comprise a decimation filter. A delay circuit provides coarse sampling phase adjustments by delaying the second clock rate by a predetermined number of first-clock cycles. A counter generates the second clock rate and provides coarse sampling phase adjustments by adding or deleting cycles of the first clock to or form the second clock. A multiplexer circuit swaps the two outputs when necessary to prevent transient errors generated in the differentiators from being observed. An interpolator circuit makes fine sampling phase adjustments by interpolation to provide an output that is transient-error free. The interpolator circuit includes a bypass circuit for bypassing the first output of the multiplexer circuit for preventing transient errors from being observed.

Transient free interpolating decimator

A digital tone detector receives a modulated input signal selectively containing at least one tone signal component. Two demodulator circuits each demodulate the input signal wherein one demodulator circuit operates at the predetermined frequency of the tone and the other demodulator circuit operates at the second harmonic. When the input tone has a low spectral harmonic power, a ratio of the demodulated outputs of the two demodulators reliably detects the presence of the tone in the input signal.

Digital tone detector using a ratio of two demodulators of differing

A noise shaping modulator for use in sigma delta modulation data conversion has two or more cascaded quantization loops. A first quantization loop is operated at a first sampling frequency and one or more higher order quantization loops are operated at a second sampling frequency. Due to speed limitations of analog circuitry in the first quantization loop, a significant improvement in signal to noise ratio may be achieved in a sigma delta modulation data converter by selecting the second sampling frequency higher than the first sampling frequency.

Multi-rate cascaded noise shaping modulator

An oversampling converter for converting an analog input signal to a high resolution digital equivalent is provided. The oversampling converter uses sigma delta modulation utilizing single integration. A plurality of quantization circuits provide a plurality of output signals, each output signal containing data information and an error component. Each quantization circuit performs an integration of a difference of an input signal and a feedback signal before quantizing the integrated signal as one of the output signals. A filter, such as a decimation filter, is coupled to the converter for receiving the multiple outputs of the converter and providing a filtered converted digital output signal.

Multiple output oversampling A/D converter with each output containing

An oversampling A/D converter for high resolution data conversion is provided. An analog input signal is quantized into a digital equivalent value with a finite quantization error associated therewith in a first circuit portion. An analog low pass filter is inserted between the first circuit portion and a second circuit portion similar in function and circuitry to the first circuit portion. The second circuit portion functions to remove the error of the first circuit portion from an output signal by providing a signal component, which when added with the output of the first circuit portion cancels the error of the first circuit portion. The low pass filter provides attenuation of quantization error provided by the second circuit portion which results in an output signal with a significantly attenuated error.

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Austin, TX, United States of America

Nicholas R Van Bavel