Microsoft Technology Licensing, LLC

Nvidia Corporation

Nicholas P Wilt

Ian Buck

Colin D McCartney

Michael Dean Stokes

Gideon Andreas Yuval

Paul England

Richard S Szeliski

Stephen Estrop

Jayant B Kolhe

Julius Vanderspek

Bastiaan Aarts

Marcus Peinado

Joseph S Beda, Iii

Paolo Enrique Sabella

Sameer Avinash Nene

Nolan David Goodnight

Glenn Frederick Evans

James S Miller

Michael Brian Cox

Philip Alexander Cuadra

James Frederick Blinn

Robin Speed

Richard Hough

One or more embodiments of the invention set forth techniques to create a process in a graphical processing unit (GPU) that has access to memory buffers in the system memory of a computer system that are shared among a plurality of GPUs in the computer system. The GPU of the process is able to engage in Direct Memory Access (DMA) with any of the shared memory buffers thereby eliminating additional copying steps that have been needed to combine data output of the various GPUs without such shared access.

Method and system for providing shared memory access to graphics processing unit processes

A method for executing an application program using streams. A device driver receives a first command within an application program and parses the first command to identify a first stream token that is associated with a first stream. The device driver checks a memory location associated with the first stream for a first semaphore, and determines whether the first semaphore has been released. Once the first semaphore has been released, a second command within the application program is executed. Advantageously, embodiments of the invention provide a technique for developers to take advantage of the parallel execution capabilities of a GPU.

Tokenized streams for concurrent execution between asymmetric multiprocessors

One embodiment of the present invention sets forth a technique for associating arbitrary parallel processing unit (PPU) contexts with a given central processing unit (CPU) thread. The technique introduces two operators used to manage the PPU contexts. The first operator is a PPU context push, which causes a PPU driver to store the current PPU context of a calling thread on a PPU context stack and to associate a named PPU context with the calling thread. The second operator is a PPU context pop, which causes the PPU driver to restore the PPU context of a calling function to the PPU context at the top of the PPU context stack. By performing a PPU context push at the beginning of a function and a PPU context pop prior to returning from the function, the function may execute within a single CPU thread, but operate on a two distinct PPU contexts.

System and method for context migration across CPU threads

One embodiment of the present invention sets forth a technique for reducing the copying of data between memory allocated to a primary processor and a coprocessor is disclosed. The system memory is aliased as device memory to allow the coprocessor and the primary processor to share the same portion of memory. Either device may write and/or read the shared portion of memory to transfer data between the devices rather than copying data from a portion of memory that is only accessible by one device to a different portion of memory that is only accessible by the other device. Removal of the need for explicit primary processor memory to coprocessor memory and coprocessor memory to primary processor memory copies improves the performance of the application and reduces physical memory requirements for the application since one portion of memory is shared rather than allocating separate private portions of memory.

Zero-copy data sharing by cooperating asymmetric coprocessors

Circuits, methods, and apparatus that inhibit the collection or updating of page characteristics where such information is not useful. One example inhibits the updating of page usage information for pages that are to be kept resident in memory and not swapped to disk. The pages for which page usage or other characteristic updates are to be suppressed can be identified in a number of ways, including using a set range of addresses, bits in page directory entries, bits in page table entries, one or more address registers, or one or more segments.

Selectively inhibit page usage bit updates

One embodiment of the present invention sets forth a method for sharing graphics objects between a compute unified device architecture (CUDA) application programming interface (API) and a graphics API. The CUDA API includes calls used to alias graphics objects allocated by the graphics API and, subsequently, synchronize accesses to the graphics objects. When an application program emits a 'register' call that targets a particular graphics object, the CUDA API ensures that the graphics object is in the device memory, and maps the graphics object into the CUDA address space. Subsequently, when the application program emits 'map' and &#x201c;unmap&#x201d; calls, the CUDA API respectively enables and disables accesses to the graphics object through the CUDA API. Further, the CUDA API uses semaphores to synchronize accesses to the shared graphics object. Finally, when the application program emits an &#x201c;unregister&#x201d; call, the CUDA API configures the computing system to disregard interoperability constraints.

System and method for enabling interoperability between application programming interfaces

One or more embodiments of the invention set forth techniques to allocate a memory buffer in the system memory of a computer system that is shared among a plurality of graphics processing units (GPUs) in the computer system. The GPUs are able to engage in Direct Memory Access (DMA) with the memory buffer thereby eliminating additional copying steps that have been needed to combine data output of the various GPUs without such a shared memory buffer.

Method and system for sharing memory between multiple graphics processing units in a computer system

One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.

System and method for representing and managing a multi-architecure co-processor application program

System and method for representing and managing a multi-architecture co-processor application program

A system and method for using an array structure to abstract the addressing of device memory allows for larger amounts of device memory to be accessed compared with using conventional pointers to access a 32 bit memory space. Additionally, the memory organization may be changed for optimal performance based on the underlying memory subsystem and characteristics of the accesses without impacting the array structure.

Conserving and shaping address space with arrays

A processor, an instruction set architecture, an instruction, a computer readable medium and a method for implementing optimal per-instruction encoding of rounding control to emulate directed rounding are disclosed. In one embodiment, an apparatus designed to perform directed rounding includes an instruction decoder configured to decode an instruction, which includes a rounding control information to calculate a result boundary. The apparatus also includes a directed rounding emulator configured to adjust the result boundary to form an adjusted result boundary as a function of the rounding control bit. The adjusted result boundary establishes an endpoint for an interval that includes a result. In one embodiment, the directed round emulator is further configured to emulate a round-to-negative infinity rounding mode and a round-to-positive infinity rounding mode based on at least the single rounding control bit.

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Seattle, WA, United States of America

Nicholas P Wilt