International Business Machines Corporation

Nicholas P Sardino

Anthony Thomas Sofia

Sean Michael Carey

Christopher Carney

Robert W St John

Vern Anthony Victoria

Embodiments include techniques for detection of data offloading through instrumentation analysis, where the techniques include monitoring, via a processor, an execution of a job, and analyzing processes associated with the job to determine a pattern. The techniques also include determining whether the pattern of the job is associated with a pattern for a workload type, and classifying the job based at least in part on the determination.

Detection of data offloading through instrumentation analysis

An approach for optimizing the use of accelerators. The approach includes receiving a job request from an application. Furthermore, a network mapping is created of one or more accelerators associated with the job request based on a utilization component. The network mapping is sent to the application to utilize the one or more identified accelerators directly by the application.

Optimized network traffic patterns for co-located heterogeneous network attached accelerators

Embodiments of the invention include methods and systems for hybrid acceleration in a processing environment. Aspects of the invention include transmitting, by a first computing system to a second computing system, a request for access to an accelerator. The first computing system receives access information for a plurality of accelerators from the second computing system responsive to the request. The first computing system analyzes the access information for the plurality of accelerators to identify a first accelerator from the plurality of accelerators and offloads a first processing job to the first accelerator utilizing the access information.

Hybrid acceleration in a processing environment

In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on.

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Hyde Park, NY, United States of America

Nicholas P Sardino