Ansys, Inc.

Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Clk Design Automation, Inc.

Nicholas Lee Rethman

Joao Moreno Geada

Nevine Nassif

James Arthur Farrell

Harry Ray Fair, Iii

William J Grundmann

Madhav Desai

Roy Badeau

Qian Shen

Murat R Becer

Ankur Gupta

Lee La France

Methods and systems for performing timing analysis during the design of a circuit are described. In one embodiment, a simulation system can generate an effective resistance value (or an impedance value based on the effective resistance value) for an instance and use the effective resistance value in a simulation to determine a minimum timing delay for the instance when only the instance switches during such simulations.

Voltage impacts on delays for timing simulation

Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit layout is received, the integrated circuit layout including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit layout based on a vulnerability characteristic of the vulnerable cell. A power analysis of a portion of the integrated circuit layout is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.

Systems and methods for accurate voltage impact on integrated timing simulation

A system for circuit timing analysis includes a database for holding results of execution of portions of a timing analysis computation. Multiple computation modules are configured for concurrent execution of the portions of a timing analysis computation, for example, a static circuit timing analysis computation. A control subsystem is coupled to the database and to the computation modules, and is configured to receive results of the portions of the computation from the computation modules and to update the database using the received results. Based on the received results, the control module selects further portions of the computations for computation and assign each selected portion to one of the computation modules. The system makes use of parallel processing that is arranged in a way that avoids bottlenecks, such as at least some memory access bottlenecks resulting from data structure locking.

Multi-engine static analysis

The present invention relates to a method and apparatus for determining capacitances and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

Timing verifier for MOS devices and related method

A method of data compression for continuous or piecewise linear curves in two variables is presented which can guarantee that any compression error is exclusively on one selected side of the curve. Limiting errors to one side is required when simulating integrated circuit performance to determine if a design will have speed-related problems. In such a simulation it is necessary to calculate both the minimum and maximum possible time delays for a logic chain of circuit elements. Data compression of the transistor or gate voltage versus time relationship is necessary to reduce the very large amount of data that is required for the simulation. Data compression may introduce errors into the data in either direction. If it is necessary to have any possible error confined to one side of the curve, the compressed data must be shifted toward the desired error side by at least the maximum possible data error. This shifting increases the total error between the compressed data and reality by more than is acceptable in current simulations. The present method approximates the data curve with piecewise linear segments all of which are on a selected side of the curve, for example the late side. This avoids increasing the error between the data curve and the stored approximation due to shifting of the stored data to ensure that all points are on the selected side.

Method to compress a piecewise linear waveform so compression error occurs on only one side of the waveform

The present invention relates to a method and apparatus for determining capacitance and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

An efficient method is presented for automatically verifying test patterns devised to detect speed critical faults in electrical circuits, with minimal human intervention. The method provides a controlled momentary inversion of a logic value at a control point within the circuit being tested or simulated, and then checks the measured or simulated circuit's output value. If the momentary logic inversion causes an inverted logic output, then the test pattern under evaluation has been determined to be capable of detecting circuits that have failures due to speed critical problems. With such an arrangement it is possible to determine whether specific test patterns will accurately measure the performance of circuit paths that have potential operating speed related problems.

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North Andover, MA, United States of America

Nicholas Lee Rethman