Nxp Usa, Inc.

Nicholas Justin Mountford Spence

John J Vaglica

James Eric Scott

Hung Hoa Tran

Yuhang Zhu

Jorge Ernesto Perez Chamorro

A controller for a one-time-programmable (OTP) memory is configured to, in response to a write request to program a single bit of an OTP value to the OTP memory, program a bit of the OTP value in the OTP memory, generate a set of PCBs corresponding to the OTP value, and program the PCBs into the OTP memory. Each PCB of the set of PCBs is generated as a logic function of a different subset of bits of the OTP value. The logic function only results in each PCB being programmed or remaining programmed in the OTP memory but not cleared. The OTP controller may be configured to, in response to the write request, program both the bit of the OTP value and a redundant bit, in which the set of PCBs includes a first PCB based on the bit and a second PCB based on the redundant bit.

One-time-programmable (OTP) memory with error detection

Digitally controllable elements capable of influencing operation of a power amplifier module are coupled in parallel to a serial data interface. Each digitally controllable element includes address control logic that decodes an address presented on the serial data interface as well as a device specific ID. In response to the decoding, physical registers in different digitally controllable elements are written in an interleaved order according to an interleaved register address map. Banks of registers within the digitally controllable elements may be select to influence or modify operation of the power amplifier module.

Methods and systems for serial control with interleaved register mapping

Digitally controllable elements capable of influencing operation of a power amplifier module are coupled to an interface gateway device using a first serial data interface that communicates using a first serial protocol. The interface gateway device receives serial data on multiple external serial data interfaces that utilize various serial protocols, and converts the various serial protocols to the first serial protocol. Each digitally controllable element includes address control logic that decodes an address presented on the first serial data interface as well as a device specific ID. In response to the decoding, physical registers in different digitally controllable elements are written.

Methods and systems for lightweight multiprotocol gateway and bridge

A communication system includes a digital data processor that produces a digital data sample and one or more control bits. A serialized transmit interface assembles the digital data sample and the control bit(s) into first and second data packets of a data frame, and sends the data frame over a signal line. A serialized receive interface receives the data frame and produces a reconstructed digital data sample and the control bit(s) from the first and second data packets. A control circuit coupled to the serialized receive interface produces a control signal from the control bit(s). The communication system may include a converter circuit, which produces an RF input signal by performing a digital-to-analog conversion of the reconstructed digital data sample, and by upconverting the resulting analog data sample signal to RF. A power amplifier amplifies the RF input signal and modifies operation of a sub-circuit based on the control signal.

Methods and systems for communicating data and control information over a serial link

A communication system includes a digital data processor that produces a digital data sample and one or more control bits. A serialized transmit interface combines the digital data sample and the control bit(s) into one or more data packets and sends the data packet(s) over a signal line. A serialized receive interface receives the transmitted data packet(s) from the signal line and produces a reconstructed digital data sample and the control bit(s) from the transmitted data packet(s). A control circuit coupled to the serialized receive interface produces a control signal from the control bit(s). The communication system may include a converter circuit, which produces an RF input signal by performing a digital-to-analog conversion of the reconstructed digital data sample, and by upconverting the resulting analog data sample signal to RF. A power amplifier amplifies the RF input signal and modifies operation of a sub-circuit based on the control signal.

A defrosting system includes an RF signal source, one or more electrodes, a transmission path between the RF signal source and the electrode(s), and an impedance matching network coupled along the transmission path. A system controller may modify the impedance matching network to reduce the reflected signal power. The system controller may determine an initial estimate of the mass of the load. Desired signal parameters for the RF signal may be determined based on the initial estimated mass of the load. The system controller may determine a refined estimate of the load mass based on a rate of change of an S11, VSWR, or reflected power parameter measured at the transmission path, or based on elapsed time between matches. Refined signal parameters for the RF signal may be determined based on the refined estimated mass.

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Phoenix, AZ, United States of America

Nicholas Justin Mountford Spence