Tokyo Electron Limited

Tel Epion Corporation

International Business Machines Corporation

Tokyo Electron Limi Ted

Nicholas Joy

Kai-Hung Yu

Kandabara N Tapily

Gerrit J Leusink

Robert Daniel Clark

David L O'Meara

Cory Wajda

Soo Doo Chae

Jeffrey Smith

Angelique Denise Raley

Sergey Alexandrovich Voronin

Kaoru Maekawa

Noel Russell

Yusuke Yoshida

Christopher Talone

Joshua LaRose

Takahiro Hakamata

Hirokazu Aizawa

Gyanaranjan Pattanaik

Christopher Catano

Alok Ranjan

Nathan P Marchack

Sebastian Ulrich Engelmann

Katie Lutker-Lee

Jodi Grzeskowiak

Qingyun Yang

Steven P Caliendo

Masanobu Igeta

Yan Shao

Luis Fernandez

Vincent Lagana-Gizzo

Allen J Leith

Vincent Gizzo

Devi Koty

Ying Trickett

Karthikeyan Pillai

Eric Chih Fang Liu

David Rosenthal

A method for processing a substrate that includes: depositing a filling material over the substrate including a first recess and a second recess, the filling material filling the first recess and the second recess; patterning the filling material such that the first recess is reopened while the second recess remains filled with the filling material; filling the first recess with a conductive material to a first height; etching the filling material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.

Method of conductive material deposition

A method for patterning a substrate includes: forming a first photoresist etch mask with an extreme ultraviolet (EUV) lithography process, the first photoresist etch mask including first through openings, the first photoresist etch mask including a metal-based photoresist material; forming a second photoresist etch mask over the first photoresist etch mask, the second photoresist etch mask including second through openings; and forming first openings, through the first and the second photoresist etch masks, in a region of the substrate that vertically overlaps both the first through openings and the second through openings.

Method for patterning a substrate using photolithography

A method of plasma processing that includes maintaining a plasma processing chamber between 10° C. to 200° C., flowing oxygen and nitrogen into the plasma processing chamber, where a ratio of a flow rate of the nitrogen to a flow rate of oxygen is between about 1:5 and about 1:1, and etching a ruthenium/osmium layer by sustaining a plasma in the plasma processing chamber.

Methods for etching metal films using plasma processing

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

Method for filling recessed features in semiconductor devices with a low-resistivity metal

A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.

Method of bottom-up metallization in a recessed feature

In accordance with an embodiment, a method of plasma processing includes etching a refractory metal by flowing oxygen into a plasma processing chamber, intermittently flowing a passivation gas into the plasma processing chamber, and supplying power to sustain a plasma in the plasma processing chamber.

Method of patterning a metal film with improved sidewall roughness

A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.

Method for selective etching at an interface between materials

Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.

Methods to protect nitride layers during formation of silicon germanium nano-wires in microelectronic workpieces

A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.

Platform and method of operating for integrated end-to-end CMP-less interconnect process

A process is provided in which low-k layers are protected from etch damage by the use of a selectively formed protection layer which forms on the low-k layer. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. In one embodiment, the selectively formed protection layer may be formed by a selective deposition process which selectively forms layers on the low-k dielectric but not over the conductor layer. The selectively formed protection layer may then be utilized to protect the low-k layer from a plasma etch that is utilized to recess the conductor. In this manner, a conductor (for example metal) may be recessed in a low-k dielectric layer via a plasma etch process.

Method of protecting low-K layers

A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.

Ruthenium metal feature fill for interconnects

A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.

Method of integrated circuit fabrication with dual metal power rail

A system and method for performing location specific processing of a workpiece is described. The method includes placing a microelectronic workpiece in a beam processing system, selecting a beam scan size for a beam scan pattern that is smaller than a dimension of the microelectronic workpiece, generating a processing beam, and processing a target region of the microelectronic workpiece by irradiating the processing beam along the beam scan pattern onto the target region within the beam scan size selected for processing the microelectronic workpiece.

Method for high throughput using beam scan size and beam position in gas cluster ion beam processing system

A method for correcting a surface profile on a substrate is described. In particular, the method includes receiving a substrate having a heterogeneous layer composed of a first material and a second material, wherein the heterogeneous layer has an initial upper surface exposing the first material and the second material, and defining a first surface profile across the substrate. The method further includes setting a target surface profile for the heterogeneous layer, selectively removing at least a portion of the first material using a gas cluster ion beam (GCIB) etching process, and recessing the first material beneath the second material, and thereafter, selectively removing at least a portion of the second material to achieve a final upper surface exposing the first material and the second material, and defining a second surface profile, wherein the second surface profile is within a pre-determined tolerance of the target surface profile.

Method of surface profile correction using gas cluster ion beam

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Albany, NY, United States of America

Nicholas Joy