Honeywell International Inc.

Honeywell G.m.b.h.

Nicholas J Wilt

Scott L Gray

Grant A Gordon

Joseph J Nutaro

Mitch Fletcher

Steven R Thompson

Brendan Hall

Larry James Yount

Thom Kreider

Aaron Raymond Larson

Byron F Birkedahl

Desi D Stelling

Allan E Harris

Dave Bibby

Brent A Morin

Robert J Aleksa

Bryan H Hill

Donald A Peterson, Jr

Norman M Atkin

Michael W Bartels

Art McCready

A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit.

Integrated dissimilar high integrity processing

A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores.

Multi-core processing cache image management

Methods and apparatus are provided for a Universal functionality Module (UFM). The apparatus comprises a programmable logic device (PLD) configured to be reprogrammed in real time and a means for universally interfacing the PLD with any effectuator device. The UFM loads a startup personality bit stream from a boot memory, which allows it to read a pin configuration associated with a effectuator device. The UFM receives a function personality associated with the pin configuration, writes the function personality to programmable logic device, and initiates the function personality.

Universal functionality module

Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

High integrity data bus fault detection using multiple signal components

Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.

Multiple-port memory systems and methods

Methods and systems for a scalable self-checking processing platform are described herein. According to one embodiment, during an execution frame, a first processing element executes both a high-criticality application and a first low-criticality application. During that same execution frame, a second processing element executes both the high-criticality application and a second low-criticality application. The high-criticality application output from the first processing element is compared with that from the second processing element before the next execution frame, and a fault occurs when the output does not match. The low-criticality application is not duplicated or compared. This and other embodiments allow high-criticality applications to be appropriated checked while avoiding the over-dedication of resources to low-criticality applications that do not warrant self-checking.

Scalable self-checking processing platform including processors executing both coupled and uncoupled applications within a frame

Systems and methods for bounded minimal latency for network resources without synchronization are provided. In one embodiment, a method for managing data traffic between nodes in an asynchronous network comprises: receiving a data request message at a first port of network switch; storing information about the data request message in a memory at the network switch; forwarding the data request message to a producer node; receiving a data message at a second port of the network switch; determining whether the data message is responsive to the data request message; when the data message is responsive, forwarding the data message from the network switch; and when the data message is not responsive, blocking the data message from being forwarded from the network.

Bounded minimal latency for network resources without synchronization

A communication network is provided. The network includes a least one switch and a plurality of ports. Each port is in communication with the at least one switch. At least one of the ports is configured to introduce a time delay after each transmission of a frame based at least in part on a maximum transmission rate of the at least one port and its allocated transmission rate.

Port rate smoothing in an avionics network

A method for initializing a chain of non-initialized data collectors is disclosed. The chain of non-initialized data collectors are coupled to a controller. In a first step communication between the controller and each data collector in the chain of non-initialized collectors is disabled, except for an active non-initialized data collector, The active non-initialized collector is coupled to the controller and any remaining non-initialized data collectors. Next, the active non-initialized data collector is initialized by assigning an identification number to the active non-initialized data collectors. The active non-initialized collector becomes an initialized data collector. Then, communication is restored between the initialized data collector and a next active non-initialized data collector in the chain of non-initialized data collectors. The method repeats until all non-initialized data collectors are initialized.

Method for sensor initialization in a structural health management system

Apparatus and systems are provided for dual redundant avionics networks wherein a remote data concentrator (RDC) includes, but is not limited to, a line replaceable unit (LRU) input, a first processing lane coupled to the LRU input, a second processing lane coupled to the LRU input, and a processor coupled to the first processing lane and the second processing lane. The first processing lane has a first output. The second processing lane has a second output. The processor has a link coupling the first processing lane with the second processing lane and is configured to route data from at least one of the first output and the second output to an Ethernet. The link is configured to transfer data between the first processing lane and the second processing lane.

Dual lane connection to dual redundant avionics networks

A method is disclosed wherein a plurality of sensors mounted on a structure, a baseline data set for each of the plurality of sensors and a calibration procedure verify the integrity of a structural health management system. Initially a baseline data set is established. Before performing the structural health assessment a calibration-in data set for each of the plurality of sensors is collected. The calibration-in data set is compared to the baseline data set for each sensor of the plurality of sensors. If the calibration-in data set and the baseline data set match then a structure characterization is performed. If the calibration-in data set and the baseline data set do not match, a calibration-out procedure is performed to generate a calibration-out data set. If the calibration-out data set and the calibration-in data sets match, then a determination is made that the structural health management system was working.

Method for satisfying certification requirements and verifying the integrity of structural health management systems

A transducer for use in a structural health monitoring system includes a single transducer element. The transducer includes a transmit assembly coupled to the single transducer element. This assembly is configured to produce a multi-cycle square wave drive signal for stimulating the transducer. Additionally, a transmit/receive switch coupled to the single transducer element is provided. This assembly is configured to isolate the drive signal from the receive assembly used to sense the electrical signal generated from any received elastic waves.

Drive, transmit & receive circuit for structural health monitoring systems

A structural health management system is disclosed. The structural health management system comprises a zone of sensors. A first sensor data collector is coupled to a first subset of the sensors in the zone; and a second sensor data collector coupled to a second subset of the sensors in the zone. In the present invention, loss of a sensor data collector does not result in the loss of ability to perform nondestructive testing in an entire zone.

Structural health management system and method for enhancing availability and integrity in the structural health management system

Methods and system for facilitating a computing platform to recover quickly from transient multi-bit data failures within a run-time data memory array in a manner that is transparent to software applications executing on the computing platform. A fault-tolerant digital computing system is provided for that utilizes parallel processing lanes in a lockstep architecture. Each processing lane includes error detectors that are configured to detect multi-bit data errors in each processing lane's memory arrays. Upon detection of a multi-bit data failure, an interrupt is generated wherein control logic software responds to the interrupt and corrects the data errors in the memory array of each processing lane.

High integrity recovery from multi-bit data failures

A capacitor is charged and discharged through switch selectable resistors from regulated DC voltage supplies and clamping diodes to provide the bias signal to control the rise and fall times of the RF output pulse of a PIN diode attenuator. An isolation buffer isolates charging and discharging transients from the bias signal. An adjustable AC gain and adjustable DC offset inverting amplifier provides the isolation buffered signal to a high impedance, very low output AC impedance source for driving the bias input of the PIN diode attenuator. The DC offset is provided by an adjustable regulated voltage source coupled to the inverting amplifier.

Growing community of inventors

Glendale, AZ, United States of America

Nicholas J Wilt