Xilinx, Inc.

Nicholas J Sawyer

James M Simkins

John D Logue

Terence J Magee

Andrew K Percey

Catalin Baetoniu

Shawn K Morrison

In an apparatus relating generally to the communication of data, a first and a second receive path block are respectively coupled to receive a first and a second data stream. A clock signal source is coupled to provide at least one clock signal to each of the first and the second receive path block. A control block is coupled to receive a first output signal pair and a second output signal pair from the first and the second receive path block, respectively. The first output signal pair includes a first crossing signal and a first data signal. The second output signal pair includes a second crossing signal and a second data signal. The control block is configured to provide first and second delay adjustment signals respectively to the first and second receive path blocks, to adjust delays of the first and second data streams, respectively.

High-speed serial data interface for a physical layer interface

A method of and apparatus for synchronous data transfer are described. The method may include encoding a clock period and data into an encoded signal, transmitting the encoded signal from a master device to a slave device, and recovering the data at the slave device without using a local oscillator. The apparatus may comprise a first integrated circuit including a master device configured to transmit an encoded signal of a clock period and data on a first port, and a second integrated circuit including a slave device where the slave device is configured to receive the encoded signal on a second port coupled to the first port and to recover the data without using a local oscillator.

Synchronous data transfer

Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay circuit is used in conjunction with a processing circuit to continuously measure the jitter of an input clock signal, thus providing clock signal performance measurement over time. In another embodiment, a pair of digital delay circuits are used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.

Method and apparatus for clock signal performance measurement

Method and apparatus for data sampling is described. More particularly, a data sampling circuit having a delay line and a plurality of tap circuits is used to sample data and provide a vector indicative of a transition region of a sampled input signal. Additionally, a hybrid sampling circuit is described with a fine grain delay line and coarse grain delay lines. Furthermore, a controller is described for using such a vector to control which data samples are used.

Method and apparatus for locating data transition regions

A self-addressing FIFO for transferring data between clock domains while avoiding the necessity of using a clock tree stores address information as bits of a data word and uses these bits to generate the next address, thus eliminating loading the clock signal with a separate counter. While data must be valid at the clock edges and the clock period still needs to be controlled, clock skew is not an issue and therefore general purpose routing may be used for the input or output clock. Users may input or output data to external devices without ever using on-board global clock resources.

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Opio, France

Nicholas J Sawyer