Ati Technologies Ulc

Nicholas J Chorney

Collis Quinn Carter

David I Glen

James Ross Goodman

Wing-Chi Chow

Yee Shun Chan

Natan Shtutman

Stephen Ho

Jonathan Wang

Minghua Zhu

A display processing device includes a display device interface and a processing unit. The processing is configured to transition at least a first component of the display processing system into a low-power state in response to an active region of a first video frame of a plurality of video frames having completed. A second component of the display processing device is configured to maintain a temporal count value corresponding to a current frame line of the plurality of video frames, and further to generate a first signal in response to the temporal count value corresponding to a first trigger value. The first signal causes the at least first component to transition out of the low-power state.

Synchronized low-power video playback

A single source image encoder encodes more than one display stream, such as multiple display streams each for a different display or multiple display streams for the same display, using multiple indexed color history (ICH) buffers. As applied to a DSC encoder, the same DSC encoder is used to encode more than one DSC compliant display stream. Multiple encoded display bitstreams are output as multiple display data streams to a plurality of displays. Such a configuration can significantly reduce the area cost of an integrated circuit that employs an image encoder since additional encoders are eliminated.

Method and apparatus for image compression that employs multiple indexed color history buffers

A single source image encoder encodes more than one display stream, such as multiple display streams each for a different display or multiple display streams for the same display, using multiple index color history (ICH) buffers. As applied to a DSC encoder, the same DSC encoder is used to encode more than one DSC compliant display stream. Multiple encoded display bitstreams are output as multiple display data streams to a plurality of displays. Such a configuration can significantly reduce the area cost of an integrated circuit that employs an image encoder since additional encoders are eliminated.

Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.

Methods and systems to reduce display artifacts when changing display clock rate

Systems and methods and computer program products are disclosed to determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method includes, forming a logical channel from a source device to a sink device where the logical channel is configured to carry the source data stream and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel. Another method includes, detecting a logical channel in a received data stream where the logical channel includes the source data stream, recovering one or more rate parameters from the received data stream, determining a data rate of the logical channel, and determining the data rate of the source data stream based on the data rate of the logical channel and the one or more rate parameters.

Embedded clock recovery

Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronizaiton, transmitter/receiver synchronization or for other control signalling.

Robust control/delineation in serial streams

Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method for transmitting a source data stream from a source device to a sink device includes, forming a logical channel from a source device to a sink device, where the logical channel is configured to carry the source data stream, and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel. A method for a sink device to recover a source data rate includes, detecting a logical channel in a received data stream where the logical channel includes the source data stream, recovering one or more rate parameters from the received data stream, determining a data rate of the logical channel, and determining the data rate of the source data stream based on the data rate of the logical channel and the one or more rate parameters. Corresponding systems and computer program products are also described.

Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronization, transmitter/receiver synchronization or for other control signalling.

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Nicholas J Chorney