Samsung Electronics Co., Ltd.

Advanced Micro Devices Corporation

Globalfoundries Inc.

Nicholas Humphries

Shawn Searles

Ashraf Ahmed

Faisal A Syed

Marc Augustin

Brian W Amick

Hanwoo Cho

Richard W Reeves

Ronald L Pettyjohn

Paul Edward Kitchin

Ryan J Hensley

Ken Yu Lim

A system and a method are disclosed to process instructions in an execution unit (EU) that includes an operand cache (OC). The OC stores a copy of at least one frequently used operand stored in a physical register file (PRF). The EU may process instructions using operands obtained from the PRF or from the OC. In the first mode, an OC renaming unit (OC-REN) indicates to the EU to process instructions using operands obtained from the OC if processing the instructions using operands obtained from the OC uses less power than using operands obtained from the PRF. In the second mode, the OC-REN indicates to the EU to process the instructions using operands obtained from the PRF if processing the instructions using operands obtained from the PRF uses less power than using operands obtained from the OC.

Register renaming of a shareable instruction operand cache

Embodiments of the present disclosure include a tininess prediction and handler engine for handling numeric underflow while streamlining the data path for handling normal range cases, thereby avoiding flushes, and reducing the complexity of a scheduler with respect to how dependent operations are handled. A preemptive tiny detection logic section can detect a potential tiny result for the function or operation that is being performed, and can produce a pessimistic tiny indicator. The tininess prediction and handler engine can further include a subnormal post-processing pipe, which can denormalize and round one or more subnormal operations while in a post-processing mode. A schedule modification logic section can reschedule in-flight operations. The schedule modification logic section can issue dependent operations optimistically assuming that a producing operation will not produce a tiny result, and so will not incur extra latency associated with fixing the tiny result in the post-processing pipe.

Tininess prediction and handler engine for smooth handling of numeric underflow

According to one general aspect, an apparatus may include a load/store unit, an execution unit, and a first and a second data path. The load/store unit may be configured to load/store data from/to a memory and transmit the data to/from an execution unit, wherein the data includes a plurality of elements. The execution unit may be configured to perform an operation upon the data. The load/store unit may be configured to transmit the data to/from the execution unit via either a first data path configured to communicate, without transposition, the data between the load/store unit and the execution unit, or a second data path configured to communicate, with transposition, the data between the load/store unit and the execution unit, wherein transposition includes dynamically distributing portions of the data amongst a plurality of elements according to an instruction.

Streaming memory transpose operations

A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Dynamic RAM Phy interface with configurable power states

A transceiver () includes a receive circuit (), a transmit circuit (), a shared delay locked loop (DLL) (), and a controller (). The receive circuit () has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit () has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller () enables the shared DLL () for use by the receive circuit () during a receive cycle, and enables the shared DLL () for use by the transmit circuit () during a transmit cycle.

Circuit using a shared delay locked loop (DLL) and method therefor

A data driver includes a first latch (), an extension logic circuit (), and a second latch (). The first latch () has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit () has an input coupled to the output of the first latch (), a control input for receiving a control signal, and an output. The extension logic circuit () selectively delays the output of the first latch () in response to the control signal. The second latch () has an input coupled to the output of the extension logic circuit (), a clock input for receiving a second clock signal, and an output for providing an output data signal.

Data driver circuit for a dynamic random access memory (DRAM) controller or the like and method therefor

A receive circuit () includes a DLL core (), a latch (), and a DLL control circuit (). The DLL core () has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch () has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core (), and an output for providing an internal data signal. The DLL control circuit () provides the DLL clock signal to the first input of the DLL core () responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core () responsive to a processor clock signal while the receive circuit () is in a second mode.

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Austin, TX, United States of America

Nicholas Humphries