Motorola Corporation

Motorola Solutions, Inc.

Nicholas Giovanni Cafaro

Robert E Stengel

Geetha B Nagaraj

Thomas L Gradishar

Sumit Anil Talwalkar

Andrew Tomerlin

Charles R Ruelke

Joseph P Heck

Raul Salvi

Rodger W Caruthers

Ralf Hekmann

Christopher Calvo

Scott Miller

An improved superheterodyne receiver for a portable radio is provided. The receiver includes a frequency controller that applies pulse-shaped modulation to first and second LO signals in a synchronized manner. The frequency controller is steered by Artificial Intelligence (AI) based machine learning (ML) to determine first and second LOs that minimize image interference in the baseband signal.

Method and apparatus for mitigating image interference in a receiver

Systems and methods for processing radiofrequency signals using modulation duty cycle scaling. One system includes a first receive path configured to directly sample a first signal in a first frequency range. The system includes a second receive path configured to convert a second signal in a second frequency range. The second receive path includes a receive modulator operating over a duty cycle. The receive modulator is configured to adjust the duty cycle by a predetermined scaling factor.

System and method for processing radiofrequency signals using modulation duty cycle scaling

Disclosed herein are systems and methods for generating injection-locked, frequency-multiplied output signals. In an embodiment, a circuit includes a ring of a number (N) serially connected delay-buffer elements and an injection-pulse-generation circuit. Each delay-buffer element provides a time delay (D), and at least some of them have at least one pulse-locking injection port. The injection-pulse-generation circuit is configured to transmit balanced-delay injection-pulse signals&#x2014;that are generated by applying balanced-delay selection logic to a clock signal according to pulse-selection control signals&#x2014;to the pulse-locking injection ports to provide, at the ring output port, an injection-locked, frequency-multiplied output signal having a frequency that equals the reciprocal of (N*D) and that bears the same proportional relationship to the frequency of the clock signal that the period of the clock signal bears to (N*D).

Systems and methods for generating injection-locked, frequency-multiplied output signals

A synthesizer comprises a first processing unit that receives digital information relating to a required final frequency of the synthesizer and determines a primary frequency value and a corresponding frequency multiplier mode. A primary synthesizer receives the primary frequency value and an external reference frequency signal to generate a signal of the primary frequency. The synthesizer further comprises a second processing unit that receives the primary frequency value, determines a pre-charge voltage value corresponding to the primary frequency value, and transmits the pre-charge voltage value to a delay locked loop in response to a change in the primary frequency value. The delay locked loop receives the signal of primary frequency and the pre-charge value. The DLL is pre-charged to the pre-charge voltage value for a predetermined time, by opening and closing the delay locked loop to obtain fast locking of the synthesizer.

Method and apparatus for fast frequency locking in a closed loop based frequency synthesizer

A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.

Method and system for managing digital to time conversion

A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal.

Clock data recovery systems and methods for direct digital synthesizers

A DPC () includes: a frequency source () for generating a clock signal; a delay line () for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device () for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices () and a combining network. A method for use in a DPC includes: receiving () a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting () at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating () an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Method and apparatus for a digital-to-phase converter

Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Direct digital synthesizer with variable reference for improved spurious performance

A dynamically matched mixer system () for use in a direct conversion radio frequency (RF) receiver includes a frequency generator () that includes plurality of dividers () for providing differential local oscillator reference sources (Fand F) and mitigation frequency reference sources (Fand F) from reference oscillator (). A mixer () mixes the differential local oscillator reference sources (Fand F) and the mitigation frequency reference sources (Fand F) while dynamic matching units () are used for receiving the mitigation frequency reference sources and matching switching parameters of differential input signals (Iand I) and differential baseband output signals (Iand I). The frequencies of the mitigation frequency reference sources (Fand F) are selected so as to establish a non-integer relationship to the reference oscillator () for mitigating the occurrence of interference with Fand F.

Dynamically matched mixer system with improved in-phase and quadrature (I/Q) balance and second order intercept point (IP2) performance

A reconfigurable processor circuit () consistent with certain embodiments of the present invention has an array of configurable circuit blocks (), wherein certain of the configurable circuit blocks () comprise one of configurable arithmetic logic units and clocked digital logic circuits. A control processor () configures a function of a plurality of the configurable circuit blocks. A memory () stores program instructions used by the control processor (). A multiple frequency generator () receives a reference clock and synthesizes the plurality of clock signals therefrom, each clock signal being configured in frequency by the control processor (). A timing control circuit () receives the plurality of clock signals, allocates the plurality of clock signals of different frequency among the plurality of circuit blocks and routes the clock signals to the circuit blocks, wherein the timing control circuit () operates under control of the control processor ().

Reconfigurable processing circuit including a delay locked loop multiple frequency generator for generating a plurality of clock signals which are configured in frequency by a control processor

A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (), where N is an integer greater than one. N frequency extender circuits () receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers () produce N seed update values. A plurality of N seed registers () each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits () each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits () produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Multiple user reconfigurable CDMA processor

A programmable skew clock signal generator has a frequency generator circuit () consistent with the invention produces an output signal Ffrom a reference signal FA frequency accumulator () is preloaded with a preload value Pand receives one reference signal cycle as a clock signal, receives a constant Kas an input thereto, with the frequency accumulator () having a maximum count Kand producing an overflow output. A phase accumulator () is preloaded with a preload value Pand receives one overflow cycle output from the frequency accumulator () as a clock signal and receives a phase offset constant Cas an input thereto. The phase accumulator () has a maximum count Cand produces a phase accumulator () output. A delay line () is clocked by the reference signal Fand produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit () receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output Fwhose phase shift &#x3c6;relative to Fis a function of Pand P.

Programmable skew clock signal generator selecting one of a plurality of delayed reference clock signals in response to a phase accumulator output

A frequency generator () includes a direct digital synthesizer () having an accumulator (or) for providing an interim output and a digital interpolator () for interpolating the interim output to provide an output signal with reduced electromagnetic interference. The digital interpolator can include at least one converter among a digital-to-phase converter () or a digital-to-time converter (). The frequency generator can further include a digitally programmable spreading function () applied to an input of the direct digital synthesizer.

Method and apparatus for reconfigurable frequency generation

A distributed amplifier consistent with certain embodiments of the present invention has a plurality of amplifier sections through N ( ) with each amplifier section having an input and an output. A plurality of N input transmission line sections are connected in series, with inputs of the through N amplifier sections interconnected at their inputs along the series of input transmission line sections. A plurality of N output transmission line sections are also connected in series, with outputs of the through N amplifier sections interconnected at their outputs along the series of input transmission line sections. A load ( ) can be driven by an output at the Nth amplifier section ( ). A high-pass filter ( ) connects a dummy load ( ) to the output of the first amplifier section ( ). The input and output transmission line sections can, for example, be lumped element T sections and the high-pass filter can be made of a lumped element half section. To achieve the desired stability enhancement, the high pass filter section has a cutoff frequency equal to or greater than the cutoff frequency of the output transmission line sections. A similar high pass filter and dummy load can be used in the input transmission line network.

Growing community of inventors

Coconut Creek, FL, United States of America

Nicholas Giovanni Cafaro